Conducts verification of IP and/or SoC microarchitecture using formal verification tools
Creates comprehensive formal verification test and coverage plans
Develops formal proofs and reviews proofs, creates methods for verification
Collaborates with architects, RTL developers, and physical design teams
Maintains and improves existing functional verification infrastructure and methodology

Requirements

B.S. in Computer Engineering or Electrical Engineering with 3+ years of experience or M.S. with 2+ years or PhD
Experience with sequential equivalence checking in complex micro-architectures
Experience in assertion writing, checker development, coverage analysis, failure debug, root cause analysis
Knowledge of computer architecture, memory hierarchy, and management
Hands-on experience with formal verification tools like JasperGold, Questa Formal, VC Formal
Experience with a hardware modeling language (Verilog, VHDL, System Verilog)
Programming experience in C/C++, Perl, Python, Ruby, Java, TCL

Benefits

Competitive pay
Stock bonuses
Health
Retirement
Vacation

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

formal verificationsequential equivalence checkingassertion writingchecker developmentcoverage analysisfailure debugroot cause analysiscomputer architecturehardware modeling languageprogramming in C/C++, Perl, Python, Ruby, Java, TCL

Soft Skills

collaborationcommunication

Certifications

B.S. in Computer EngineeringB.S. in Electrical EngineeringM.S. in Computer EngineeringM.S. in Electrical EngineeringPhD