
Memory Debug Engineer
Intel Corporation
full-time
Posted on:
Location Type: Office
Location: Hillsboro • California • Oregon • United States
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Salary
💰 $141,910 - $269,100 per year
About the role
- Drive the enablement, validation, and complex debugging of memory subsystems
- Provide strategic oversight of memory IO interfaces
- Define and execute the overarching validation and debug strategy for memory IO interfaces
- Lead the reproduction and root-cause analysis of high-priority customer-submitted failure sightings
- Ensure all customer memory IO interfaces meet industry-standard electrical signal integrity (SI) compliance
- Define Memory Reference Code (MRC) requirements for validation and margin optimization
- Act as the primary liaison between Intel Silicon Engineering, BIOS/Firmware teams, and the customer
- Manage and drive task force environments to resolve critical bugs
- Communicate effectively with cross-functional teams and external customers
Requirements
- BS/MS/PhD in Electrical Engineering or Computer Engineering
- 4+ years of industry experience
- 3+ years of experience of DDR4/DDR5, LPDDR4/5 protocols
- 3+ years of experience of debug tools: high-speed oscilloscopes, logic analyzers, margining tools, profilers (e.g. Intel Vtune etc) and protocol exercisers
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- Competitive pay
- Stock bonuses
- Benefit programs which include health
- Retirement
- Vacation
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
memory subsystemsmemory IO interfacesvalidation strategydebug strategyroot-cause analysiselectrical signal integrityMemory Reference CodeDDR4DDR5debug tools
Soft Skills
strategic oversightcommunicationcross-functional collaborationcustomer liaisontask force management
Certifications
BS in Electrical EngineeringMS in Electrical EngineeringPhD in Electrical EngineeringBS in Computer EngineeringMS in Computer EngineeringPhD in Computer Engineering