Eightfold

Engineer

• Perform sophisticated electrical device characterization to determine electrical fail mechanisms.
• Operate fault isolation equipment to accurately narrow down failure defect locations.
• Conduct physical failure analysis to identify and classify physical defects.
• Establish and hypothesize potential electrical or process fail mechanisms based on detailed electrical fail models and physical failure analysis characterization, supporting process improvement.
• Collaborate closely with a diverse range of collaborators, including teams from frontend to backend and the Global Quality (GQ) department, to address and resolve defectivity issues.
• Prepare and present comprehensive electrical and physical failure mechanisms on a weekly basis to drive continuous improvement.
• Develop and implement new fault isolation and physical failure analysis techniques to stay ahead of industry standards.
• Coordinate the maintenance and high uptime of fault isolation and physical failure analysis tools to ensure world-class operational efficiency.

Engineer CE PYE – Physical Failure Analysis, Fault Isolation

Operations

• Support the development and maintenance of cycle time metrics, dashboards, and reports to enable performance visibility and decision-making.
• Assist in data collection, validation, and basic analysis to identify cycle time gaps, trends, and improvement opportunities across backend manufacturing sites.
• Participate in cycle time improvement projects by supporting root cause analysis, documentation, and action tracking under guidance from senior engineers/managers.
• Learn and apply standard cycle time methodologies, metric definitions, and best-known methods (BKM) used across the network.
• Support preparation of materials for regular cycle time performance reviews and working meetings with site and central teams.
• Collaborate with cross functional partners (e.g., Operations, Engineering, Planning) to understand backend manufacturing processes and business needs.
• Contribute to documentation, training materials, and knowledge sharing to support standardization and capability building.

Global Operational Excellence Cycle Time Engineer

• Develop, optimize, and transfer thin film deposition processes for EUV-enabled DRAM technology
• Lead process characterization, troubleshooting, and defect reduction through VME
• Drive thin film roadmap activities aligned to future technology nodes
• Collaborate with internal teams and suppliers to mature equipment, chemistries, and process solutions
• Analyze large physical and electrical datasets and communicate clear recommendations

Films Process Development Engineer

Content Manager

• Define and own the end-to-end show narrative, aligning BU product priorities with corporate and brand messaging
• Lead Director-level BU stakeholders through kickoff, alignment, and content lock processes across multiple shows
• Curate demo and booth content into a cohesive attendee experience, ensuring stories connect across BUs
• Develop booth staff messaging, talk tracks, and lead pre-show training to ensure confident, consistent storytelling
• Deliver executive-ready post-show recaps and manage post-event content in partnership with PR, social, and amplification teams

Global Event and Trade Show Content Lead

Project Manager

• Manage innovative projects in memory and storage solutions
• Lead global, cross-functional initiatives
• Develop benchmarks and governance frameworks
• Cultivate strong connections with management and colleagues

Operation Portfolio Management Office Project Manager

• Own High NA EUV scanner performance including availability, reliability, efficiency, and matching
• Lead equipment lifecycle activities such as installation, PM strategy, upgrades, fixing issues, and documentation
• Drive monitoring and improvement of imaging stability, overlay, focus, defectivity, and source performance
• Partner with vendors, NYCreates, facilities, and PAC teams on equipment, safety, and infrastructure requirements
• Act as technical authority for advanced numerical aperture EUV, offering mentorship, training, and recommendations to engineers and leadership

EUV Scanner Engineer

• Develop and integrate photolithography unit processes for advanced memory technologies
• Perform material evaluations, reticle and layout development, OPC, overlay optimization, and process window analysis
• Drive yield improvement, failure analysis, and device performance optimization
• Partner with equipment vendors to evaluate tools and improve process capability
• Document processes, communicate results, and support technology transfer to manufacturing

Semiconductor Process Engineer – Photo

Compliance

• Manage the process for screening transactions for restricted end-uses, end-users, and end-destinations
• Support the implementation of screening the Watchlist/Sanctioned Party List (SPL) platform by conducting due diligence
• Manage processes for resolving licenses and help prepare and submit any required export licenses or authorizations
• Manage the process for the sale of used semiconductor manufacturing equipment to ensure compliance
• Lead global trade compliance projects, driving standardization, process improvement, and scalability across regions
• Partner with IT and business collaborators to deliver enterprise processes/system integration and automation
• Support program governance, timelines, milestones, risks, and success metrics
• Support and manage integration of export compliance processes with enterprise systems
• Help develop and implement risk assessments and audits
• Support internal/external audits and regulatory inquiries by gathering documentation
• Develop and maintain SOPs, work instructions, controls, and records retention practices for EUC/OCR workflows
• Establish and monitor KPIs and drive continuous improvement
• Develop and deliver role-based export compliance training for global partners
• Support other initiatives and projects as provided by global trade compliance leaders.

Lead Principal Trade Compliance

Mechanical Engineer

• Define and implement full-chip floorplans in collaboration with analog and digital teams
• Execute place and route, timing closure, and ECOs through final sign-off
• Own static timing, power integrity, and physical verification closure
• Integrate scan and support DFT and ATPG execution
• Coordinate with foundry and document PD decisions for follow-on designs

Staff Physical Design Engineer

Designer

• Define and execute the full-chip DV plan including coverage targets and sign-off criteria
• Build and maintain UVM/SystemVerilog testbenches for soft IP and top-level integration
• Develop directed and constrained-random tests and close functional and code coverage
• Apply assertions and formal methods for control logic, CSR correctness, and CDC checks
• Support post-silicon bring-up with debug data, test vectors, and documentation

Design Verification Engineer

Civil Engineer

• Lead structural design and construction support for advanced semiconductor manufacturing, cleanroom, and support facilities across U.S. sites, ensuring alignment with stringent operational, seismic, and contamination control requirements.
• Develop and review structural systems including foundations, slabs‑on‑grade, superstructures, steel and concrete framing, and equipment support structures for vibration‑sensitive cleanroom environments.
• Perform and oversee structural analysis and design for gravity, lateral, seismic, wind, and equipment loads in accordance with governing codes and semiconductor‑specific performance criteria.
• Collaborate with multidisciplinary teams (Civil, Architectural, MEP, and Process Engineering) to integrate CSA systems into complex semiconductor facility designs.
• Prepare and review detailed structural drawings, specifications, calculations, and delegated design packages for steel, concrete, and specialty structural systems.
• Support construction teams during execution by resolving structural design issues, reviewing RFIs and submittals, and providing field engineering support as needed.
• Manage structural design scope, schedule, and coordinating closely with project managers, estimating teams, and construction partners.
• Ensure compliance with local building codes, seismic requirements, safety laws, and internal semiconductor facility standards through rigorous design reviews and organizational change processes.
• Participate in bid evaluations, cost estimating, value engineering, and contractor selection for structural work packages.
• Provide technical feedback for permitting, authority‑having‑jurisdiction (AHJ) coordination, and regulatory reviews related to structural and seismic design.

Senior Structural Engineer – Global Facilities

• Design custom analog blocks with a primary focus on PLL, DLL, and clock recovery circuits
• Contribute to PHY-level analog architecture and performance trade-off decisions
• Build and run transistor-level simulations including corner and mismatch analysis
• Partner with layout and digital teams to define clean mixed-signal interfaces
• Support silicon bring-up and correlate measurements to simulation results

Principal Analog Design Engineer – Mixed-Signal PHY, Clocking, High-Speed I/O

Financial Planning and Analysis

• Support MCBU monthly P&L results and forecast reviews with BU leadership.
• Build and maintain dashboards and key performance indicators (KPIs) to track business performance.
• Prepare executive-level MCBU Finance presentations for senior leadership (e.g., CBO, GM, and BU leadership forums).
• Support quarterly and annual planning cycles, including outlooks, operating plans, and long-range plans.
• Perform profitability analysis by market segment, technology, product, and customer.
• Identify low-margin products, customers, or segments through review of trends in financial data.
• Perform and validate product cost analyses, including variances analysis and cost change impacts.
• Partner closely with MCBU Business Operations, Pricing, Product Management, and Product Lifecycle Management to deliver informed financial analysis.
• Support monthly business reviews by preparing executive review materials and identifying variances to plan.
• Support ad-hoc financial analyses, product cost deep dives, and special projects.
• Contribute to continuous improvement of financial processes, tools, and reporting methodologies.

Senior Financial Analyst – MCBU Finance

• Develop and oversee global electrical and equipment safety programs and standards
• Act as Micron’s technical expert for electrical and equipment safety, covering complex and high-risk systems
• Consistently interpret and implement SEMI S2, NFPA 79, and IEC 60204-1 across sites and suppliers
• Lead and approve electrical safety documentation reviews and third-party assessments
• Influence safe-by-design outcomes through cross-functional and supplier engagement

Global EHSS Principal Electrical Safety Engineer

• Define chip-level digital architecture and integrate hard macros with soft IP
• Own RTL design for control logic, registers, clocking control, and top-level integration