Principal Analog Design Engineer – Mixed-Signal PHY, Clocking, High-Speed I/O

Eightfold

Principal Analog Design Engineer designing original analog circuits for mixed-signal PHY clocking. Shaping future interface architectures by pushing performance limits in analog design.

Posted 4/29/2026full-timeBoise • California, Idaho, Texas • 🇺🇸 United StatesLead💰 $159,000 - $347,000 per yearWebsite

About the role

Key responsibilities & impact

Design custom analog blocks with a primary focus on PLL, DLL, and clock recovery circuits
Contribute to PHY-level analog architecture and performance trade-off decisions
Build and run transistor-level simulations including corner and mismatch analysis
Partner with layout and digital teams to define clean mixed-signal interfaces
Support silicon bring-up and correlate measurements to simulation results

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering or related field, with MS or PhD strongly preferred
10+ years of analog or mixed-signal IC design experience with primary tape-out ownership
Deep expertise in clocking circuits such as PLLs, DLLs, or CDRs in advanced CMOS
Strong transistor-level simulation skills using HSpice or equivalent tools
Experience defining analog-digital interfaces and initialization behavior

Benefits

Comp & perks

Medical, dental and vision plans
Income protection programs
Paid family leave
Robust paid time-off program
Paid holidays

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

analog designmixed-signal IC designPLLDLLclock recovery circuitstransistor-level simulationcorner analysismismatch analysisanalog-digital interfacesinitialization behavior

Certifications

Bachelor's degree in Electrical EngineeringMS in Electrical EngineeringPhD in Electrical Engineering