Eightfold

Full-stack Engineer

• Leverage powerful AI tools to support the successful completion of your internship project assignments.
• Creating and integrating intuitive user experiences into our software applications.
• Developing/enhancing solutions that solve business needs.
• Enhancing and providing support for existing solutions that are adding value.
• Generating proactive monitoring and usage metrics that establish system baselines to be able to predict future demands.
• Communicating and collaborating with peer groups to ensure our software meets internal standards.

Intern – Software Engineer

• Drive best-in-class product maturity which includes bits per wafers (yield), product grades (Repair Density and DPM) at the fastest speed and cycle of learning
• Collaborate with YE, Device, RDA, Metrology team to resolve top yield issues, develop inline visibility to enable fast yield ramp and minimize excursion
• Identify best known method and business process from DRAM/NAND sites and drive for alignment and standardize across network

FE CPIE PI Principal/Staff Engineer

Artificial Intelligence

• Own and evolve the CMBU AI roadmap in alignment with Micron’s enterprise AI strategy and governance
• Identify and deliver high‑value AI, automation, and advanced analytics solutions that address real business problems
• Lead complex transformation initiatives end‑to‑end, from concept through deployment and adoption
• Drive adoption of Micron‑approved AI platforms through enablement, playbooks, and training
• Track, measure, and communicate business impact across productivity, cycle time, and adoption metrics

AI & Digital Transformation Lead

Mechanical Engineer

• Contribute to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits
• Perform circuit modeling, sensitivity analyses, and assist in developing validation through widely recognized simulation software and tools
• Design on-silicon test chips and lead required tape-out revisions
• Coordinate and collaborate with the layout team, including floor-planning, placement, and routing
• Carry out verification procedures with modeling and simulation using industry-standard simulators

Principal Design Engineer, Pathfinding

Solutions Engineer

• Own the long‑term strategy for optical interconnect across pluggable optics, onboard/near‑package optics, and co‑packaged optics
• Define system‑level architecture direction and guide tradeoffs in power, bandwidth density, latency, thermal design, reliability, and cost
• Lead technical engagements with hyperscalers and ecosystem partners, including architecture studies and system‑level prototypes
• Deliver competitive and market insights across lasers, silicon photonics, DSPs, optical switches, packaging, and manufacturing
• Support corporate development with technical due diligence, integration assessments, and investment recommendations

Senior Principal Data Center Solutions Architect

Software Engineer

• Define and drive the medium‑ to long‑term technology vision for high‑performance storage in evolving system architectures
• Identify and shape new business opportunities through collaboration with engineering, operations, and ecosystem partners
• Lead Quarterly Technology Reviews and strategic tech engagements with customers and partners
• Represent the company in industry organizations, standards bodies, and public forums
• Analyze market and competitive trends to guide roadmap and product differentiation

Senior Member of Technical Staff, Core Data Center

Application Engineer

• Establish relationships and influence with key decision makers at focus customers
• Enable development of differentiated solutions and products based on technology challenges driving customer’s business objectives
• Act as an advisor to our customers by providing memory architecture advice, memory product recommendations, delivering technical trainings and developing solutions
• Regularly visit customers to identify new business, discuss ongoing projects including areas of concern & future needs
• Assist in solving problems and providing test support; be the central point of contact during critical issues between customer and factory teams
• Work with development teams to evaluate feasibility of specific new products or features and ensure customer specifications are met
• Coordinate lab-related activities that support the design-in/validation process, including schematic/board layout reviews, design validation and system level testing
• Continually meet, track, train and help external partners including authorized external rep and industrial distribution teams which directly cover non-focus customers.

Staff Application Engineer, Broadmarket

Designer

• Develop and complete verification plans for SoC-level and subsystem builds
• Develop verification components including UVM agents, scoreboards, checkers, assertions, and coverage models
• Drive functional coverage closure
• Verify complex IP integrations
• Collaborate with RTL designers to debug functional issues
• Participate in SoC-level integration verification
• Leverage hardware emulation/acceleration platforms
• Support post-silicon validation and debugging

Principal SoC Design Verification Engineer, HBM

Product Manager

• Support product requirements, specifications, and roadmaps for HBM products
• Collaborate with engineering, manufacturing, quality, and supply chain teams in Asia
• Contribute to customer enablement and new product introduction activities
• Assist with financial and business analysis
• Gather and analyze market, industry, and competitive information

Product Manager, New College Grad

• Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die
• Integrate internal and third-party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic)
• Collaborate with SoC architects to translate architectural and micro-architectural specifications into high-quality RTL implementations
• Participate in SoC-level integration activities, including clocking, reset, power intent, and configuration infrastructure
• Support design verification through debug of simulation, emulation, and formal results; resolve functional, performance, and connectivity issues
• Work closely with physical design teams to address synthesis, timing, power, and floor planning considerations
• Assist with pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues
• Contribute to design documentation, block specifications, and design reviews
• Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds
• Continuously improve build quality, reusability, and development efficiency through established guidelines and automation

SoC Design Engineer

• Implement layout changes to resolve issues identified on current HBM designs on silicon and drive towards a timely and efficient tapeout.
• Interact with teams like DE, PE, PI and TD to understand the challenges due to process limitations and propose layout solutions to alleviate the issues.
• Be proactive in identifying and flagging design issues, performance problems, and opportunities to improve design performance and reduce power consumption.
• Responsible for floor plans that optimize circuit placement, signal routing, and power delivery.
• Deliver block-level (analog or mixed signal) layouts using advanced foundry process node if needed.
• Contribute to the development of new HBM product opportunities by assisting with the overall planning and optimization of Memory, Logic, and Analog circuits layout.
• Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products.
• Mentor new hires as needed.

Staff Physical Design Engineer, HBM

• Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
• Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
• Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
• Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
• Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
• Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
• Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.

HBM SoC Physical Design Engineer

• Own end-to-end SSD controller project execution, from architecture definition through silicon bring-up
• Work with multi-functional teams and drive alignment across hardware, firmware, and system integration
• Define and track project plans, achievements, and risks
• Drive technical decision-making for SSD controller features
• Manage execution readiness and all work involved, including specs, reviews, tape-out readiness
• Communicate project status clearly to leadership

MTS ASIC Design Engineer

Operations

• Develop, implement, and maintain manufacturing methods
• Estimate manufacturing cost and time standards
• Maintain records and reporting systems for manufacturing operations

Global AT Operational Excellence – Cycle Time Engineer

Manager

• Act as a key liaison between Finance and construction teams
• Partner with our global team of regional Construction Controllers
• Facilitate cross-functional collaboration
• Attend construction project meetings to collect real time views of progress, risks, and opportunities
• Highlight opportunities to reduce risk and improve cost, schedule, and cashflow
• Generate and maintain project dashboards on construction cost, schedule, cashflow and risk
• Ensure accurate reporting of actual and forecast values. Evaluate and explain variances
• Maintain financial transparency across construction projects
• Partner with construction teams to develop accurate baseline and forecasted costs
• Validate estimates and improve forecast accuracy
• Collect and maintain historical data including costs, schedules, and scope
• Drive for best-in-class construction and facility cost by understanding competitive benchmarks and internal objectives
• Improve capital allocation processes compliance (e.g. initial approvals and change management) to achieve greater value for the company
• Develop budget walks and lessons learned with construction teams during project execution and at project completion
• Leverage and align construction and capital finance tools (Procore, SAP, Snowflake)
• Ensure adherence with Micron construction processes across jurisdictions
• Participate in project control improvement efforts leveraging best practices
• Analyze project data and reports to identify risks and opportunities