Cirrus Logic

Designer

• Join silicon design verification team and work closely with digital/analog designers, applications engineers, and manufacturing test.
• Participate in all aspects of verification for complete mixed-signal IC developments.
• Work on complex verification systems and contribute to improvements in verification methodology.

Senior Design Verification Engineer

• Design complex, multi‑layer, high-density interconnect PCBs, consisting of multiple lamination cycles and via structures, from schematic capture through manufacturing release.
• Translate schematics, system requirements, and signal‑integrity constraints into robust, manufacturable board layouts at sub 0.4 mm pitch.
• Drive high‑speed design practices, including impedance‑controlled routing, differential pair tuning, length matching, and power‑integrity optimization.
• Collaborate closely with IC design, packaging, hardware, mechanical, and engineering teams to ensure seamless integration across the full product stack.
• Adhere to DFM, DFF, DFT, resolve manufacturability issues, and ensure compliance with industry standards and internal quality guidelines.
• Oversee the generation of fabrication and assembly documentation, including Gerbers, ODB++, drawings, and build notes.
• Champion continuous improvement in design workflows, automation, and tool utilization to increase efficiency and design quality.

Senior PCB Designer

Engineer

• Collaborate with systems and design teams to facilitate top down design methodology, architectural exploration and mixed signal integration.
• Work with chip and DV leads to plan, setup, & execute DMS & AMS verification.
• Contribute to a team that generates & verifies advanced analog circuit equivalent models to support analog design, UVM verification, & HW/SW validation platforms
• Collaborate with system architects and designers to streamline architectural exploration of next-generation IP
• Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM), User-defined Types(SV-UDT), & Verilog AMS
• Develop DMS & AMS test plans, test benches, and verification methodologies to verify microarchitectures
• Collaborate with multi-functional teams to streamline chip-level integration and maintain continuity of design, verification, and modeling feature drop plans
• Serve as a primary mixed signal design regression debug support
• Develop DMS & AMS test platforms and execute DMS & AMS test plans
• Contribute to analog design reviews and recommend enhancements for improved circuit design and partitioning
• Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow
• Contribute to development of automation tools for design, verification and modeling

Senior Staff Analog Mixed Signal Modeling & Verification Engineer

• You will contribute to a team that generates & verifies advanced analog circuit equivalent models to support analog design, UVM verification, & HW/SW validation platforms
• Collaborate with system architects and designers to streamline architectural exploration of next-generation IP
• Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM), User-defined Types(SV-UDT), & Verilog AMS
• Develop DMS & AMS test plans, test benches, and verification methodologies to verify microarchitectures
• Collaborate with multi-functional teams to streamline chip-level integration and maintain continuity of design, verification, and modeling feature drop plans
• Serve as a primary mixed signal design regression debug support
• Develop DMS & AMS test platforms and execute DMS & AMS test plans
• Contribute to analog design reviews and recommend enhancements for improved circuit design and partitioning
• Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow
• Contribute to development of automation tools for design, verification and modeling