Cirrus Logic

Formal Verification Engineer, Co-Op

Cirrus Logic

internship

Posted on:

Location Type: Hybrid

Location: Austin • Texas • United States

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Job Level

Entry Level

Tech Stack

PerlPython

About the role

  • Support the formal verification team to follow, and improve, defined methodology practices.
  • Develop test plans and verification methodologies to formally verify the microarchitecture and design.
  • Perform failure analysis and resolution, coverage analysis, and population.
  • Implement and improve functional and formal verification.

Requirements

  • Master’s or PhD degree in Electrical or Computer Engineering
  • Knowledge in designing and implementing verification environments for module-level designs.
  • Proficiency in System Verilog.
  • Familiarity with scripting languages such as Python, Perl, TCL, Bash.
  • Experienced or knowledge in UVM or equivalent methodologies.
  • Knowledge in formal property languages such as SVA.
  • Knowledge in property-based model-checking.
  • Knowledgeable in signal processing, analog or digital design fundamentals.
Benefits
  • Interns should expect to be in the office more often, up to 5 days per week, based on business needs and team preference.
  • Meaningful community engagement and delivering enjoyable employee experiences at every turn.
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
System VerilogUVMPythonPerlTCLBashformal property languagesSVAproperty-based model-checkingsignal processing
Certifications
Master’s degree in Electrical EngineeringMaster’s degree in Computer EngineeringPhD in Electrical EngineeringPhD in Computer Engineering