FREE ACCESS
5,000–10,000 jobs/day
See all jobs on JobTailor
Search thousands of fresh jobs every day.
Discover
- Fresh listings
- Fast filters
- No subscription required
Create a free account and start exploring right away.
Formal Verification Engineer, Co-Op
Cirrus Logic. Support the formal verification team to follow, and improve, defined methodology practices.
Tech Stack
Tools & technologiesPerlPython
About the role
Key responsibilities & impact- Support the formal verification team to follow, and improve, defined methodology practices.
- Develop test plans and verification methodologies to formally verify the microarchitecture and design.
- Perform failure analysis and resolution, coverage analysis, and population.
- Implement and improve functional and formal verification.
Requirements
What you’ll need- Master’s or PhD degree in Electrical or Computer Engineering
- Knowledge in designing and implementing verification environments for module-level designs.
- Proficiency in System Verilog.
- Familiarity with scripting languages such as Python, Perl, TCL, Bash.
- Experienced or knowledge in UVM or equivalent methodologies.
- Knowledge in formal property languages such as SVA.
- Knowledge in property-based model-checking.
- Knowledgeable in signal processing, analog or digital design fundamentals.
Benefits
Comp & perks- Interns should expect to be in the office more often, up to 5 days per week, based on business needs and team preference.
- Meaningful community engagement and delivering enjoyable employee experiences at every turn.
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
System VerilogUVMPythonPerlTCLBashformal property languagesSVAproperty-based model-checkingsignal processing
Certifications
Master’s degree in Electrical EngineeringMaster’s degree in Computer EngineeringPhD in Electrical EngineeringPhD in Computer Engineering