Cirrus Logic

Mechanical Engineer

• Responsible for all aspects of physical implementation from RTL to GDS, including RTL synthesis, scan stitching, timing constraints creation, Power analysis, chip floor plan, clock distribution, full chip assembly, Timing driven Placement & Route, Static Timing Analysis, timing closure, ECO and tapeout.

Physical Design Engineer

Application Engineer

• Provide direct engineering support for Cirrus Logic customers and field personnel
• Develop reference designs and demonstration platforms
• Develop application notes, white papers, demo-board, and reference-design manuals
• Develop firmware and RTL modules for customer reference and demonstration
• Implement customer-application focused data collection and circuit analysis
• Collaborate and communicate closely with IC Design engineers, Systems engineers and Validation engineers to understand and define design requirements and customer use cases.
• Autonomously manage tasks and priorities
• Travel approximately 2 weeks per year, domestically and abroad

Applications Engineer – Rotation Program

SDET

• Design and develop test plans for new features and products (both black box and white box) by translating requirements into test cases and incorporating customer feedback into test plans.
• Implement tests during the pre-silicon and post-silicon phases of the product.
• Own the communication with cross-functional teams and represent the team in discussions and reviews.
• Drive toward automation of all tests within a Continuous Integration environment.
• Find issues and triage/debug them with software teams.
• Present results to product owners, internal customers, and software developers to assist in resolving defects.

Senior Staff Embedded Software Test Engineer – NG

• Design high-performance delta-sigma ADCs and DACs
• Participate in the design of various classes of amplifiers, DC/DC converters, and other circuitry
• Develop CMOS mixed-signal circuitry from concept to production
• Model analog circuits in Matlab, Verilog-A, and SystemVerilog
• Simulate and verify circuit performance and functionality using Spectre and Maestro
• Simulation and verification at the chip level using analog-on-top and digital-on-top methodologies

Senior Staff Analog Design Engineer

Designer

• Join silicon design verification team and work closely with digital/analog designers, applications engineers, and manufacturing test.
• Participate in all aspects of verification for complete mixed-signal IC developments.
• Work on complex verification systems and contribute to improvements in verification methodology.

Senior Design Verification Engineer

• Design complex, multi‑layer, high-density interconnect PCBs, consisting of multiple lamination cycles and via structures, from schematic capture through manufacturing release.
• Translate schematics, system requirements, and signal‑integrity constraints into robust, manufacturable board layouts at sub 0.4 mm pitch.
• Drive high‑speed design practices, including impedance‑controlled routing, differential pair tuning, length matching, and power‑integrity optimization.
• Collaborate closely with IC design, packaging, hardware, mechanical, and engineering teams to ensure seamless integration across the full product stack.
• Adhere to DFM, DFF, DFT, resolve manufacturability issues, and ensure compliance with industry standards and internal quality guidelines.
• Oversee the generation of fabrication and assembly documentation, including Gerbers, ODB++, drawings, and build notes.
• Champion continuous improvement in design workflows, automation, and tool utilization to increase efficiency and design quality.

Senior PCB Designer

Engineer

• Collaborate with systems and design teams to facilitate top down design methodology, architectural exploration and mixed signal integration.
• Work with chip and DV leads to plan, setup, & execute DMS & AMS verification.
• Contribute to a team that generates & verifies advanced analog circuit equivalent models to support analog design, UVM verification, & HW/SW validation platforms
• Collaborate with system architects and designers to streamline architectural exploration of next-generation IP
• Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM), User-defined Types(SV-UDT), & Verilog AMS
• Develop DMS & AMS test plans, test benches, and verification methodologies to verify microarchitectures
• Collaborate with multi-functional teams to streamline chip-level integration and maintain continuity of design, verification, and modeling feature drop plans
• Serve as a primary mixed signal design regression debug support
• Develop DMS & AMS test platforms and execute DMS & AMS test plans
• Contribute to analog design reviews and recommend enhancements for improved circuit design and partitioning
• Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow
• Contribute to development of automation tools for design, verification and modeling

Senior Staff Analog Mixed Signal Modeling & Verification Engineer

• You will contribute to a team that generates & verifies advanced analog circuit equivalent models to support analog design, UVM verification, & HW/SW validation platforms
• Collaborate with system architects and designers to streamline architectural exploration of next-generation IP
• Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM), User-defined Types(SV-UDT), & Verilog AMS
• Develop DMS & AMS test plans, test benches, and verification methodologies to verify microarchitectures
• Collaborate with multi-functional teams to streamline chip-level integration and maintain continuity of design, verification, and modeling feature drop plans
• Serve as a primary mixed signal design regression debug support
• Develop DMS & AMS test platforms and execute DMS & AMS test plans
• Contribute to analog design reviews and recommend enhancements for improved circuit design and partitioning
• Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow
• Contribute to development of automation tools for design, verification and modeling

Staff Analog Mixed Signal Modeling & Verification Engineer

Architect

• Define the end-to-end architecture for ML accelerators and SoCs, including compute fabrics, dataflows, memory hierarchies, and integration with mixed-signal front ends.
• Translate domain-specific requirements (voice interaction, sensor analytics, motor control) into architectural specifications and accelerator designs.
• Lead architectural exploration of performance, power, area, and cost tradeoffs; create models and benchmarks for workload-driven analysis.
• Collaborate closely at the instruction set and compiler/toolchain level to ensure that the ISA, micro-architecture, and runtime stack are co-optimized for ML workloads and domain-specific kernels.
• Partner with internal engineering, startups, and research institutions to rapidly prototype candidate architectures on FPGA/ASIC platforms and validate with representative workloads.
• Define and evaluate on-chip security architectures, including trusted execution environments (TEE), enclaves, memory partitioning, and hardware root-of-trust, ensuring robust protection for ML-enabled SoCs.
• Evaluate external IP, startups, and research in ML accelerators; identify opportunities for partnership, licensing, or incubation.
• Serve as a technical advisor across multiple CVL initiatives; mentor engineers, guide innovation managers, and influence long-term compute strategy.
• Work backwards from customer problems to ensure architectures are not only performant, but also scalable, integrable, and monetizable in real-world systems.
• Publish architectural principles, drive internal alignment around ML-enabled mixed-signal processing, and represent CVL in industry and academic forums.

Principal SoC Architect – ML Accelerators

• Bench test, debug, and characterization of embedded on-chip circuitry (amplifiers, data converters, power converters, etc.) to ensure functionality and performance as per the datasheet.
• Design, develop, and debug silicon validation and characterization board-level hardware and bring-up the platforms prior to first silicon.
• Develop automated test framework and regression test suites in Python to optimize validation efficiency.
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to Cirrus Logic backend test methodologies.
• Collaborate closely with Design Engineers, Systems Engineers, and Application Engineers to understand requirements and use cases.
• Analyze test results and identify failures/defects using business intelligence tools such as Spotfire, Excel and JMP.
• Support and develop automation software for test equipment including NI STS / PXIe platforms and bench-top instruments.
• Write technical reports/summaries of all data collected.

Graduate Validation and Characterization Engineer

• Participate in all aspects of digital verification for complete mixed signal IC developments
• Work on complex verification systems
• Contribute towards improvements in verification methodology

Design Verification Engineer – NWB

• participate in all aspects of digital verification for complete mixed signal IC developments
• work on complex verification systems
• contribute towards improvements in verification methodology within Cirrus Logic

Design Verification Engineer – EDI

QA Engineer

• In this position, you will be the “voice of the customer” responsible for Customer Quality interactions across multiple customers and will work closely with multi-functional teams across the organization to drive ongoing improvements in quality processes to support our customers.
• You will directly interface with leaders across all function to enable world-class product development, qualification, implementation, and execution of best practices, and will significantly impact our programs by being the voice of the customer within the quality function.

Customer Quality Engineer

• Design digital logic circuits and digital filters for applications including Mixed Signal Audio converters and amplifiers, Embedded SoC, Power/Energy Management, high precision Industrial/Data Acquisition products.
• Design using Verilog, logic simulation, functional verification, & synthesis of DSP & data conversion ICs in a mixed signal environment.
• Implement RTL modules; perform integration and integrated functional verification; performing behavioral modeling of analog and mixed signal circuits, vector generation testing, and lab test development.

Senior Staff Digital Design Engineer

• Design and build FGPA rapid prototyping platform to accelerate early firmware development for mixed-signal SoCs.
• Collaborate closely with hardware and software teams.
• Validate and test the prototyping platform, ensuring functional correctness and robustness.
• Optimize platform performance and capacity for firmware development.