Drive New Product Introduction for established silicon technologies
Support mixed-signal IC development from initial design to early volume, leading new product tape-out, driving early yield optimization and supporting product qualification
Work with IC design, marketing, and product engineering teams to establish product silicon technology needs
Establish relationship with foundry suppliers to guide development of base technology and to develop custom silicon modules or devices in support of Cirrus Logic roadmap
Work with cross-functional teams to solve multi-faceted performance and yield issues on complex mixed-signal ICs
Support IC design and layout teams with specialist process knowledge, advising and reviewing SOA use conditions and design rule compliance, including DFM
Requirements
Bachelor's/Master’s/PhD degree in Electronics, Physics, Materials Engineering, or equivalent
7+ years in semiconductor technologies
Detailed knowledge of device physics, and experience with device characterization
Proven background in planar technology development, process integration, or technology transfer with knowledge of 180nm to 22nm processes
Experience with semiconductor manufacturing issues, trade-offs, and yield improvement activities, including DFM methodologies
Detailed knowledge of device physics and reliability (e.g. HCI, TDDB, SOA characterization, etc.)
Strong data analysis skills with an analytical approach to assessing and identifying alternative courses of action for resolution of unique and diverse technical problems
Knowledge of key analog & mixed-signal design, device and design rule requirements (e.g. noise, mismatch, Rdson, multiple voltage domains, etc.) and associated process implications
Ability to handle multiple projects, and work efficient as part of a team or independently
Available for up to 15% travel overseas
(Preferred) Demonstrated knowledge of semiconductor manufacturing processes, procedures, facilities and equipment
(Preferred) Experience in high voltage and BCD technology development or process integration
(Preferred) Prior experience working with external foundries
(Preferred) Prior experience collaborating with PDK & Modeling teams, and familiarity with layout and design rule review
(Preferred) Test chip design and bench characterization experience