Salary
💰 $110,000 - $150,000 per year
About the role
- Architect and generate ASIC/FPGA test benches
- Generate test cases and run simulations to verify the functionality of ASIC/FPGA code
- Generate and perform testing on target hardware as part of post-silicon validation or integrated test environment (Hardware in the Loop)
- Collect functional and code coverage metrics
- Validate and verify ASIC/FPGA requirements
- Help debug ASIC/FPGA design and/or test issues
- Prepare materials for peer reviews and major program design reviews
Requirements
- 3+ years’ experience with SystemVerilog Universal Verification Methodology (UVM), Pyuvm or similar verification methodology
- Experience with COCOTB and python-based HDL simulations
- Experienced in running ASIC/FPGA simulations using QuestaSim, VCS, Riviera-Pro, or Verilator
- Experienced in collecting ASIC/FPGA coverage metrics
- Experienced in defining test plans, generating test cases and testbench components
- Experienced in writing VHDL, Verilog or SystemVerilog code for ASIC/FPGA design
- Experience in Python scripting, simulations and tool development
- ASIC/FPGA design experience (preferred)
- Digital circuit design experience (preferred)
- Experience with constrained random test benches (preferred)
- Experienced with assertion-based simulations (preferred)
- Experience validating DSP-centric designs (preferred)
- Experience running back-annotated ASIC/FPGA simulations (preferred)
- US CITIZENSHIP, PERMANENT RESIDENCY, REFUGEE OR ASYLUM STATUS IS REQUIRED.
- Unlimited PTO - Vacation, Sick, Personal, and Bereavement
- Paid Parental and Adoptive Leave
- Medical, Dental and Vision Insurance
- Tax Advantage Accounts (HSA/FSA)
- Employer Paid Short and Long Term Disability, Basic Life, AD&D
- Additional Benefit Options Including Voluntary Life and Emergency Medical Transport
- EAP Program
- Retirement Savings Plan - Traditional 401(k) and a Roth 401(k)
- Equity Grants in the Company
ATS Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
SystemVerilogUniversal Verification Methodology (UVM)PyuvmCOCOTBVHDLVerilogQuestaSimVCSRiviera-ProVerilator