Salary
💰 $196,000 - $368,000 per year
About the role
- Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) to increase chip frequency while minimizing power across internal tools
- Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction
- Own the whole process from discovery and invention of new optimization opportunities to developing solutions and working directly inside design teams to facilitate deployment
- Write high-capacity, fast software and collaborate with design teams to deploy tools on the latest processes and advanced designs
- Work across parallel computing, machine learning, and specialized algorithms for VLSI design to advance internal EDA tools
Requirements
- BS, MS, PhD or equivalent experience in Electrical Engineering or Computer Science
- 12+ years in VLSI algorithms development using C++
- Strong understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.
- Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC
- Familiarity with typical design flows written in Perl, Tcl, and Python
- Strong communication and interpersonal skills
- C++14 or newer experience (lambdas and concurrency) (preferred)
- Detailed understanding of how multiple Physical Design steps interact and how they can be fused to form hybrid engines (preferred)
- Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use (preferred)
- Experience with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks applied to physical design (preferred)
- Highly driven to craft outstanding software towards improving PPA with a dedication to continuous improvement (preferred)