Salary
💰 $136,000 - $212,750 per year
Tech Stack
AssemblyPerlPython
About the role
- Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes
- Develop flows for advanced place and route methods, floorplanning and chip assembly, power and clock distribution, power and area optimization, timing, IR and EM analysis and closure
- Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all our product lines
Requirements
- Pursuing a MS in Electrical or Computer Engineering (or equivalent experience)
- Understanding of physical design optimization and routing methodologies at place, cts, route and postroute, especially power and area efficient setup and hold optimization
- Experience in advanced Clock tree synthesis methods and techniques
- Strong background in STA, extraction, timing and RC correlation
- Background with design rules in advanced nodes and their impact on DRC closure and PPA optimization
- Understanding of power intent files such as UPF, and use of FSDB/SAIFs for power optimization
- Understanding of hierarchical design, pinning and budgeting flows
- Experience with power distribution networks, Design for Yield and Manufacturability, EM and IR closure and thermal management
- Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++
- Understanding of AI/ML methods in physical design optimization is preferred
- Knowledge of industry standard EDA tools, with proficiency in Innovus based flows preferred