Salary
💰 $196,000 - $368,000 per year
About the role
- Invent and optimize new methods for floorplanning and chip-level optimization tools
- Develop machine learning strategies to improve efficiency of design space exploration
- Explore high performance algorithms for block placement, datapath estimation and other details of early design estimation
- Explore use of LLMs, GNNs, GANs, and Reinforcement Learning for efficient EDA solutions
- Write code and own the whole process from discovery and invention to final deployment of solutions
- Define new projects, explore technical domains, and drive the roadmap of hardware design productivity
Requirements
- MS or PhD in Electrical Engineering or Computer Science or equivalent experience
- 10+ years of EDA software and VLSI hardware design
- Proven track record in software development with C++, particularly in algorithm development related to graph, placement, optimization, analysis and visualization
- Familiarity with related EDA techniques, including floorplanning, placement, routability, partitioning, static timing analysis, and SAT solvers
- C++17/C++14 experience, such as lambdas and concurrency
- Deep understanding of algorithm design principles such as complexity analysis, multithreading, distributed computing, efficient memory and I/O use
- Experience in chip level floorplanning, timing estimation and design optimization
- Familiarity with various machine learning techniques for analysis, optimization, and use of AI code generation tools
- Good communication and interpersonal skills