University of Washington, Department of Electrical & Computer Engineering

Mechanical Engineer

• Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan
• Work closely with the analog and digital design teams on floor planning and signal distribution
• Coordinate with program managers to track layout and floorplan activities
• Conduct layout reviews and complete full-chip closure activities
• Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks
• Participate in the IC layout methodology roadmap

Senior Staff Design Engineer, IC Layout