Senior Staff Design Engineer, IC Layout

University of Washington, Department of Electrical & Computer Engineering

Senior Staff Design Engineer creating RFID and Reader IC floorplans at Impinj. Collaborating with global teams on complex IC projects, ensuring quality and efficiency in production.

Posted 7/23/2026full-timeRemote • 🇺🇸 United StatesSenior💰 $158,700 - $238,100 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in custom analog, RF, and mixed-signal layout with a strong focus on full-chip/SOC-level floorplanning and integration. Proven ability to lead complex IC projects from conception to tapeout while mentoring layout engineers and managing technical projects.

Highest-signal resume keywords

Custom Analog LayoutRF LayoutMixed-Signal LayoutFull-Chip/SOC-Level FloorplanningTechnical Project Management

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Transistor-Level LayoutRF Circuit DesignAnalog Circuit DesignFloorplan MethodologySignal Distribution

Soft Skills

LeadershipMentoringCollaboration

Tools & Technologies

IC Layout ToolsLayout Review Tools

Industry Keywords

Semiconductor Manufacturing ProcessesFoundry TechnologiesAdvanced Process NodesTapeout

About the role

Key responsibilities & impact

Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan
Work closely with the analog and digital design teams on floor planning and signal distribution
Coordinate with program managers to track layout and floorplan activities
Conduct layout reviews and complete full-chip closure activities
Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks
Participate in the IC layout methodology roadmap

Requirements

What you’ll need

Bachelor’s or master’s degree in computer or electrical engineering or a related technical field, with 12+ years of experience
Experience in custom analog, RF, and mixed-signal layout, with ability to lead complex ICs from conception to tapeout
Expert in full-chip/SOC-level floorplanning and integration
Understanding of semiconductor manufacturing processes and foundry technologies across advanced process nodes down to 16nm
Strong technical project management skills
Ability to lead and mentor other layout engineers

Benefits

Comp & perks

Health insurance
401(k) plan and company match
Merit increases
Annual bonus
Stock options
Open paid time-off policy