SiTime

Senior Principal Analog Mixed-Signal Design Engineer

SiTime

full-time

Posted on:

Location Type: Office

Location: Minato-ku • 🇯🇵 Japan

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Job Level

Senior

About the role

  • Contribute to the architectural definition of the design and chip integration
  • Technical leader for chip level design and verification simulations to ensure building blocks meet specifications at the schematic level and after post-layout extraction, while fully provisioning for DFT and DFM
  • Work closely with Layout Engineers to validate proper layout, using all best-known methods
  • Document assigned blocks, and hold preliminary and final design review meetings
  • Actively participate in the chip bring-up, evaluation and characterization, with emphasis on owned blocks
  • Work cross-functionally with Product, Characterization, Test, and Application Engineers on issues related to owned circuit blocks
  • Coach, mentor and develop junior/mid-level analog designers, foster cross-functional collaboration

Requirements

  • M.S. in Electrical Engineering or related field with minimum 15 years of related experience, or Ph.D. in Electrical Engineering with minimum 12 years of related experience
  • Excellent academic record with published research projects prototyped and proven in silicon
  • Detailed knowledge of CMOS circuits and noise analysis
  • Core expertise in one of the following areas: Integer-N and fractional-N PLL, Sigma-Delta ADCs, Temperature sensor, Analog and digital filters, Quartz or MEMS oscillator, Sub-threshold circuits, Low noise regulator and bandgap, High-speed output drivers
  • Ability to oversee circuit layout for critical blocks
  • Knowledge of programming languages: MATLAB, VerilogA
  • Proficient in using Cadence analog design tools
  • Good facilitation skill for project/design review meeting
  • Excellent analytical, problem-solving, written/verbal communication. Proven leadership and ability to collaborate across system architects, digital teams, layout, test, manufacturing
Benefits
  • In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals
  • Equity grants, providing a meaningful opportunity to share in the company's future growth and success

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard skills
CMOS circuitsnoise analysisInteger-N PLLfractional-N PLLSigma-Delta ADCsTemperature sensorAnalog filtersDigital filtersLow noise regulatorHigh-speed output drivers
Soft skills
leadershipcollaborationanalytical skillsproblem-solvingcommunicationfacilitation
Certifications
M.S. in Electrical EngineeringPh.D. in Electrical Engineering