Senior Engineer, Verification
SiTime
full-time
Posted on:
Location Type: Office
Location: Minato-ku • 🇯🇵 Japan
Visit company websiteJob Level
Senior
Tech Stack
PerlPython
About the role
- Developing SV-RNM models for both analog and mixed-signal circuits
- Developing verification plan from chip or block specifications
- Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.) Developing digital-top verification in System Verilog
- Defining and writing System Verilog Assertions (SVA)
- Defining and writing functional coverages and covergroups
- Running simulations and debugging simulation results
- Reviewing verification results for Tape-out sign-off
- Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas
Requirements
- MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of work experience doing verification in the semiconductor industry
- Good verbal and written communication skills in English
- Proficient in SystemVerilog and SystemVerilog OOP
- Fluency in utilizing scripting languages such as Perl / Python
- Proficient (through work experience) in verification using UVM
- Strong experience writing SystemVerilog Assertions (SVA)
- Understanding of Analog schematic and experience with Cadence Virtuoso
- Basic understanding of digital design using Verilog
- Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers
- Ability to work independently and drive solutions to challenging problems
- Desired Qualification: Experience with generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS), or similar techniques
- Experience with UVM-AMS methodology
- Solid experience with Formal Property Verification (FPV)
- Programming experience writing OOP code in C++
Benefits
- In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact.
- We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
System VerilogUVMSystem Verilog Assertions (SVA)functional coveragescovergroupsscripting languagesPerlPythonFormal Property Verification (FPV)C++
Soft skills
verbal communicationwritten communicationteamworkproblem-solvingindependencecollaboration