SiPearl

Senior IP Subsystem SoC Architect

SiPearl

full-time

Posted on:

Location Type: Hybrid

Location: Massy • France

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Job Level

Senior

Tech Stack

Python

About the role

  • Define IP, subsystem and SoC architectures to meet performance, silicon area, cost and manufacturing constraints
  • Break down architectures into functional sub-blocks and write high-level architecture specifications, including interfaces and configuration mechanisms
  • Participate in commercial IP selection and process technology choices
  • Provide detailed definitions of software programming and configuration interfaces
  • Support RTL, physical design, verification, virtual and software prototyping teams by clarifying architectural intent and constraints
  • Review microarchitecture specifications, verification strategies and validation plans
  • Interface closely with marketing and product teams to ensure architectural alignment with roadmap and customer needs
  • Contribute to technology intelligence, monitoring standards, market trends and emerging technologies
  • Represent the company at seminars, conferences and technical forums, and share key learnings internally
  • Take ownership of work packages in collaborative and partnership projects, acting as a technical point of contact
  • Coordinate project deliverables and contribute regularly to partner exchanges
  • Mentor, coach and technically supervise junior engineers, trainees and service providers
  • Contribute to effort estimation, milestone planning, onboarding and training programs
  • Support the manager in supervising team members within the defined scope

Requirements

  • Extensive experience in complex chip architecture and microarchitecture
  • Strong background in electronic engineering, microelectronics or computer engineering
  • Ability to translate market and product requirements into robust technical architectures
  • Professional proficiency in English in an international environment
  • Scientific rigor, attention to detail and strong analytical capabilities
  • Experience in the following areas is a strong plus:
  • Core architecture design, PCIe, UCIe, memory interfaces
  • Cache architectures, memory consistency models, Network-on-Chip (NoC)
  • Communication protocols and system-level integration
  • Advanced ASIC design flows and semiconductor technologies
  • Strong software background and hardware/software co-design
  • Proficiency in scripting languages (Python, TCL, etc.)
  • Leadership roles in collaborative or multi-partner projects
Benefits
  • annual bonus*
  • meal vouchers (60% covered by SiPearl)
  • health insurance (70% covered by SiPearl)
  • illimited access and pre-paid sessions with a practitioner of your choice on our mental health partner app, moka.care
  • technical, linguistic and personal development training
  • BSPCE
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
chip architecturemicroarchitecturecore architecture designPCIeUCIememory interfacescache architecturesNetwork-on-Chip (NoC)communication protocolsASIC design
Soft Skills
analytical capabilitiesattention to detailleadershipmentoringcollaborationcommunicationownershipproject coordinationscientific rigortechnical supervision