Silvaco Inc

Manager

• Lead architecture, circuit design, and physical implementation of memory compilers across SRAM, ROM, 1-port and 2-port register files, and dual-port RAM.
• Define bitcell selection, peripheral architecture (decoders, sense amps, write drivers, IO, self-timing), redundancy and repair strategy, and assist circuits (read/write assist, body bias) to hit aggressive PPA targets.
• Drive Vmin, leakage, performance, area, and yield optimization across PVT corners, process variation, and aging effects.
• Own the technical roadmap for the memory portfolio: new compiler variants, new nodes, feature enhancements, and methodology improvements.
• Establish design, verification, and signoff methodology, while leading design and layout reviews, SPICE/FastSPICE characterization, statistical/Monte Carlo analysis, BIST/repair, DFT, and physical verification.
• Lead silicon validation efforts including test chip development, testing and reporting.
• Lead, mentor, and grow a team of memory design engineers spanning circuit design, layout, characterization, and compiler/automation.
• Set individual and team goals, conduct technical reviews, and develop career paths for engineers at multiple levels.
• Allocate engineering effort across roadmap projects, customer commitments, and silicon programs; manage schedules, dependencies, and risk.
• Build a culture of design rigor, peer review, and continuous methodology improvement.
• Serve as the senior technical lead in presales engagements — qualifying opportunities, presenting Silvaco's memory portfolio, and shaping winning technical proposals.
• Translate customer SoC requirements (frequency, voltage, density, power, port configuration, special modes) into compiler specifications and PPA commitments.
• Partner with sales, field application engineers, and product management on RFQs, technical evaluations, and competitive benchmarking.
• Lead deep-dive technical workshops with customer architects and design teams; respond to detailed technical questionnaires and audit-style reviews.
• Own PPA analysis across the memory portfolio — performance, power (active and leakage), area, and yield — at both the instance and SoC-aggregate level.
• Build and maintain competitive benchmarks against foundry and third-party memory IP; identify gaps and prioritize closure.
• Drive what-if and sensitivity analysis to guide architecture trade-offs (e.g., bitcell choice, mux ratio, banking, assist circuits, voltage operating range).
• Translate PPA insights into clear, customer-ready collateral: datasheets, application notes, and technical white papers.
• Act as the primary technical point of contact for strategic customers throughout the engagement lifecycle — from evaluation through integration, tapeout, and silicon validation.
• Lead technical reviews, integration debug, and silicon correlation discussions with customer design and product engineering teams.
• Drive root-cause analysis and resolution of customer-reported issues, coordinating across design, characterization, CAD, and product teams.
• Represent Silvaco in foundry partner meetings and at industry conferences as needed.

Senior Manager, Embedded Memory