Positions are open for full-time in the ares of physical design and integration from sub-system level to full chip level, involving all aspects of physical design partition and integration functions.
Requirements
Experience in design partitioning, budgeting, pin planning with multiple takeout experience
Knowledge using synthesis, place & route, analysis and verification CAD tools.
Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL
Good understanding of device physics and experience in deep sub-micron technologies
Knowledge of Verilog and SystemVerilog
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.