NVIDIA

Full-stack Engineer

• Establish yourself as a technical specialist in AI networking products, specifically the BlueField DPU and ConnectX product lines
• Architect, design, and develop innovative, scalable, and high-performance hardware-accelerated software solutions
• Lead deep technical engagements with hyperscalers, involving design-in, coding, bring-up, performance tuning, failure analysis, and production hardening
• Partner with internal engineering, product, and architecture teams to transform customer needs into product features, reference architectures, tooling, and guidelines
• Drive performance, reliability, and debuggability improvements across customer stacks and translate findings into actionable product, firmware, and software roadmap items

Senior Software Engineer, AI Networking

LLM Engineer

• Lead and grow a team responsible for specialized kernel development, runtime optimizations, and frameworks for LLM inference
• Drive the design, development, and delivery of production inference software, targeting NVIDIA's next-generation enterprise and edge hardware platforms
• Integrating cutting-edge technologies developed at NVIDIA and offering an intuitive developer experience for LLM deployment
• Lead software development execution, with responsibility for project planning, milestone delivery, and cross-functional coordination

Manager, Large Language Model Inference

Software Engineer

• Managing a team of experienced compiler and performance engineers
• Establish team objectives to meet schedules and goals
• Act as a mentor and advisor to grow our next generation of leaders
• Establish and evolve policies and procedures that affect the immediate organization
• Communicate with senior management for team vision and development

Manager, Compiler Engineering

Engineer

• Validate the industry’s leading processors for deep learning, gaming, and high-performance computing.
• Understand the design and implementation and bridge your knowledge to bring-up and productization
• Manage the validation of chip features and lead debug of observations on Silicon.
• Responsible for developing and productizing ATE functional vectors
• Work multi-functionally with ASIC, SW, System, Characterization and ATE teams to accomplish your tasks.

Senior Silicon Validation Engineer

• Work on crafting creative Signal Integrity solutions to complex system design problems.
• Modeling and Optimization of vias, connectors, sockets, breakouts and various system components in 3D EM tools.
• System-level signal integrity simulations of high-speed NVlink 200Gbs+, USB-4, PCIe5, GDDR6, LP5X and other interfaces.
• Constant improvements of SI models using data from lab measurements and/or modelling tool/methodology updates.
• Substrate and board layout SI guidelines creation, review and post layout SI extractions.
• Simulation automation, data gathering, analysis and visualization using JMP, MATLAB or similar tools.
• Opportunity to work in a dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit.

Signal and Power Integrity Engineer, New College Grad

Artificial Intelligence

• Analyze full‑chip and unit‑level power using internal and industry‑standard RTL and gate‑level power tools, and translate data into concrete design and architectural improvements.
• Develop and productionize power‑aware models and flows, including ML/RL‑based techniques for anomaly detection, dynamic power management, and design‑space exploration.
• Design and train new LLMs that “learn the art” of power analysis from design data, power reports, bug histories, and best practices—so they can: Assist engineers in interpreting complex power data Propose likely root causes and candidate fixes Recommend architectural and micro‑architectural optimizations for power Perform comparative power analysis across workloads, products, and design options to identify trends, anomalies, and optimization opportunities that aren’t obvious from first principles alone.
• Partner closely with Architects, Performance, Software, ASIC Design, and Physical Design teams to interpret power data, root‑cause power bugs, and drive fixes and design changes.
• Prototype and evaluate new architectural features in Verilog, with a strong focus on their power and energy implications.
• Automate and scale flows (Python/Perl/C++), and define new pipelines that fast‑track power anomaly detection and close the loop between power data, AI models, and design decisions.
• Apply AI to power optimization: build and deploy data‑driven models—using machine learning, reinforcement learning, data analytics, and custom LLMs—to recommend or automatically tune power‑efficient configurations and policies.

Senior Power Analysis and Optimization Engineer, AI-LLM Systems

Backend Engineer

• Research and analyze existing internal distributed storage services.
• Research, design, and implement scalable, next-gen distributed storage services for HPC workloads, optimizing both performance and cost-effectiveness to meet NVIDIA’s growing infrastructure needs
• Develop tooling to automate management of large-scale infrastructure environments, to automate operational monitoring and alerting, and to enable self-service consumption of resources.
• Detail the general procedures and practices, perform technology evaluations, related to distributed file systems.
• Collaborate across teams to better understand developers' workflows and capture their infrastructure requirements.
• Influence and guide methodologies for building, testing, and deploying applications to ensure efficient performance and resource utilization.
• Supporting our researchers to run their flows on our clusters including performance analysis and optimizations of deep learning workflows
• Root cause analysis and suggest corrective action for problems large and small scales

Senior HPC Storage Engineer

Hardware Engineer

• Work on groundbreaking GPU and CPU systems.
• Understand them across a range of disciplines and identify areas for improvement.
• Study the applications and models running on Nvidia hardware and their architectural implications.
• Come up with microarchitectural solutions for connectivity, coherency, power management, security, memory management and other SOC level issues.
• Understand and help drive implementation of bus protocols, networking protocols, memory access and security solutions across a range of products.
• Work with software, firmware, platform and multi-functional teams on system architecture.
• Model, analyze, and explain the performance and power advantages of Nvidia solutions.
• Guide customers and firmware engineers to extract the most performance from microarchitectural structures.

AI Hardware Architect

• Design and develop scalable, cloud solutions to accelerate HPC and AI workloads using NVIDIA’s advanced technologies (GPUs, DPUs, ConnectX).
• Contribute to NVIDIA’s AI supercomputing platforms.
• Collaborate with cross-functional teams to deliver new features and improve existing products.
• Design and develop robust software systems.

Senior Software Engineer – Cloud, Kubernetes

• Establish groundbreaking performance benchmarking methodologies and analysis workflows and identify performance issues and opportunities for NVIDIA’s inference ecosystem (e.g. TensorRT/TensorRT-EdgeLLM/Torch-TensorRT)
• Contribute features and code to NVIDIA/OSS inference frameworks including but not limited to TensorRT/TensorRT-EdgeLLM/Torch-TensorRT.
• Develop new model pipelines for NVIDIA’s inference ecosystem with optimized performance including but not limited to areas like quantization, scheduling, memory management, and distributed inference to set the gold standard for Gen AI performance.
• Work with cross-collaborative teams inside and outside of NVIDIA across generative AI, automotive, robotics, image understanding, and speech understanding to set directions and develop innovative inference solutions.
• Scale performance of deep learning models across different architectures and types of NVIDIA accelerators.

Senior Deep Learning Software Engineer, TensorRT Performance

• Solve difficult problems at the intersection of compilers, runtime libraries, programming models, and high-performance computing architectures
• Implement new and future OpenACC, OpenMP, and standard language parallelism features for C++, Fortran, and Python for NVIDIA GPUs and Multicore CPUs
• Participate in the evolution of standard language parallelism for GPUs and Multicore CPUs
• Balance individual effort with teamwork throughout debugging, prototyping, and productization
• Discuss and refine software designs and implementation strategies with peers
• Partner with application teams to investigate interesting and meaningful compilation problems from the HPC community

HPC Compiler Developer

• Design and develop the GenAI open source Megatron Core and NeMo Framework
• Solve large-scale, end-to-end AI training and inference challenges, spanning the full model lifecycle from initial orchestration, data pre-processing, and running of model training and tuning, to model deployment.
• Work at the intersection of AI applications, libraries, frameworks, and the entire software stack.
• Innovate and improve model architectures, distributed training algorithms, and model parallel paradigms.
• Accelerate foundation model training and finetuning with mixed precision recipes and next-gen NVIDIA GPU architectures.
• Performance tuning and optimizations of deep learning framework and software components.
• Research, prototype, and develop robust and scalable AI tools and pipelines.

Senior AI Training Framework Engineer

DevOps Engineer

• You will be part of a new team of engineers who design and implement applications and sophisticated CI/CD tools, infrastructure and workflows using open-source and NVIDIA proprietary software
• Crafting efficiency and usability improvements across our group that will help streamline various release pipelines and processes across Nvidia
• Be in the critical path supporting the group developers as well as intimately understanding the values of predictability, automation and reliability

• Design and develop algorithms for map-based driving products.
• Architecture design for map provider, health monitors and data fusion with perception.
• Develop highly efficient in-vehicle code in C++14 or later.
• Design and integrate algorithmic solutions into the core of NVIDIA AV Research, and develop transformer based models tailored for graphs.
• Implement evaluation frameworks to measure performance of large scale LLM’s.
• Analyze and fine-tune SOTA pretrained models on domain specific datasets.
• Build automated map content analysis in Python, JavaScript or TypeScript.
• Create scalable and distributed map-building workflows.

Senior Software Engineer, Mapping – Autonomous Vehicles

• Owning and leading the NVOS including development, testing flow and product life cycle
• Use your expertise in C++ and Python to develop NVOS features and support new products
• Lead NVOS integrations with FW, hardware, and production teams
• Support internal and external customers for any NVOS related items