NVIDIA

Engineer

• Develop verification components and API's for cluster and system level test benches
• Verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC
• Architect the testbenches and craft verification environment using SV, C/C++ methodology
• Define test plans, tests and verification infrastructure for clusters and systems
• Build efficient and reusable bus functional models, monitors, checkers, and scoreboards
• Implement functional coverage and own SOC level verification closure
• Work with architects, designers, FPGA, and post-silicon teams to ensure robustness

Senior Verification Engineer – HSIO Cluster, SOC

• Develop UVM-based verification test benches and methodologies
• Verify ARM architecture based distributed fabric needed to transport control, sidebands and data
• Drive aspects of verification for the unit
• Architect testbenches and craft verification environment using SV and UVM
• Define test plans, tests and verification infrastructure for modules, clusters and systems
• Build efficient and reusable bus functional models, monitors, checkers, and scoreboards
• Implement functional coverage and coordinate the verification closure process for the unit
• Work with architects, designers, FPGA, and post-silicon teams

Senior Verification Engineer – ARM Fabric Unit Level

Mechanical Engineer

• Develop innovative AI-powered methodologies and applications for chip design — spanning specification, RTL, verification, and physical design
• Collaborate with chip design stakeholders across architecture, RTL, DV, FV, and physical design teams to understand existing challenges and form the best solutions
• Utilize, develop, and assimilate AI-based tools and flows into the chip design process
• Evaluate cutting-edge AI tools and EDA vendor technologies, and apply them to improve the development process
• Define and enforce design quality standards — lint rules, synthesis guidelines, and coding best practices
• Develop training sessions and guide designers with best design practices, including AI-assisted workflows
• Build automation infrastructure and scripted flows to streamline chip design development

Senior AI Chip Design Engineer

• Participate in definition and implementation of boot and chiplet control technologies
• Define, code and integrate sophisticated boot components
• Collaborate with architects, other design teams, verification, back-end and production testing
• Write micro-architecture documents and code design blocks
• Bring your design to silicon tape-out and silicon testing and production

Senior Chip Design Engineer

Solutions Engineer

• Actively promote the NVIDIA culture with partners & customers
• Activate & enable partners through hands-on workshops and ideation
• Expand partner capabilities with pre-sales support on existing and new technologies
• Build and nurture an active community of Subject Matter Experts in the partner landscape across EMEA
• Foster learning and development by sharing feedback, guidance and knowledge with sales and product specialists
• Support and provide guidance to our partners
• Deliver technical sales presentations, product demonstrations, hands-on training and proof of concepts

Partner Solutions Architect – Nordics

QA Engineer

• Review arch design and requirements documents for new features introduced in several domains like Switch/HCA/NVL/Linkx FW.
• Design, develop, and perform tests for the new features, as part of FW GA or update releases.
• Automate newly added tests in the existing automation framework, and add new capabilities and features to the framework.
• Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by R&D team, and raise if not fixed.
• Conduct tests in various areas, including regression, performance, functional, and security.
• Keep track of testing progress and generate summary reports of testing activities.
• Fully collaborate with different external teams like product marketing, R&D, and verification.
• Define and build setups topologies for appropriate product coverage.

Firmware QA Engineer

• Develop verification components and APIs for cluster and system level test benches
• Verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC
• Architect the testbenches and craft verification environment using SV, C/C++ methodology
• Define test plans, tests and verification infrastructure for clusters and systems
• Build efficient and reusable bus functional models, monitors, checkers, and scoreboards
• Implement functional coverage and own SOC level verification closure
• Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust

Security Analyst

• Lead Incident Response efforts for corporate, cloud, and product environments, including investigation, containment, eradication, and recovery.
• Perform threat hunting across endpoints, networks, and cloud workloads to proactively identify indicators of compromise, emerging threats, and control gaps.
• Conduct cloud incident response for AWS, Azure, and GCP, and other cloud environments including Kubernetes and containerized workloads.
• Drive product security incident response, collaborating with engineering teams to analyze potential exposure to vulnerabilities.
• Perform digital forensics and malware analysis to support investigations.
• Develop and optimize security orchestration and automation playbooks.
• Provide guidance to engineering and business teams on secure design and contribute to security policies and metrics.

Cyber Security Analyst

Architect

• Analyze workloads of interest on existing silicon
• Collaborate with cross-functional teams to define performance metrics
• Conduct comprehensive performance evaluations
• Propose architectural features that optimize system performance
• Act as a subject matter expert on system performance

Senior Architect – Server Performance

Designer

• Take a crucial part in developing NVIDIA's next-generation chip controller and boot.
• Design and verification with challenging multi-discipline context.
• Take part in the development of all NVIDIA's networking and GPU networking chips and systems.

Senior Chip Design Verification Engineer

• Actively promote the NVIDIA culture with partners & customers
• Activate & enable partners through hands-on workshops and ideation
• Expand partner capabilities with pre-sales support on existing and new technologies
• Build and nurture an active community of Subject Matter Experts in the partner landscape across EMEA
• Foster learning and development by sharing feedback, guidance and knowledge with sales and product specialists
• Support and provide guidance to our partners

Partner Solutions Architect – DACH, CEE Region

Full-stack Engineer

• Responsible for implementing the Unified Firmware architecture and System management software across NVIDIA server platforms.
• Leading end-to-end platform architecture, spanning hardware abstraction, firmware design, security, and scalable system management using OpenBMC.
• Hands on work with bringing up of BMC firmware, performance analysis and coding various manageability features for NVIDIA’s Server platforms.
• Developing and reviewing code, writing and reviewing design documents, reviewing QA test plan and working closely with all team members to achieve consensus for design and testability as per product requirements.
• Designing and developing performance optimized active monitoring BMC solutions using DMTF Standards including MCTP, Redfish, SPDM and PLDM specifications.
• Instrumenting code to ensure maximum code coverage, writing and automating unit tests for each implemented module and maintain detailed unit test case reports.
• Providing software quality reports based on static analysis, code coverage, CPU load.
• Working with security team to ensure developed code is in line with product security goals.
• Working closely with hardware teams to influence hardware design and review HW architecture & schematics.
• Generate API documentation from code using Swagger or similar tools.
• Help generate content for user guides to pursue customer problems etc.
• Drive product life cycles with QA teams to productize the module, and be responsible as a product owner.

Senior System Software Engineer, OpenBMC

• Engaging in the physical build of blocks according to specifications under challenging constraints, targeting efficient power, area, and performance.
• Working on a variety of exciting builds, resolving complex timing and congestion issues with precision.
• Engaging in all facets of physical chip build development (RTL2GDS), including synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
• Contributing to flow development to improve and innovate our processes.
• Collaborating with a team of outstanding engineers to achieve flawless integration and implementation of builds.

Physical Design Engineer

• Act as the lead architect for deploying the NemoClaw framework natively on Windows environments
• Guide the engineering efforts to optimize the agent runtimes for Windows
• Design the integration of NemoClaw with NVIDIA's hardware and middleware stack
• Partner closely with internal AI research teams, driver teams, and the open-source OpenClaw community
• Foster a collaborative engineering culture by mentoring senior engineers

Principal Engineer – AI Agents and Systems

Public Relations

• Support execution of strategic communications programs, helping track team priorities, manage timelines and keep initiatives moving forward.
• Help develop and implement proactive communications strategies that strengthen NVIDIA’s reputation and help mitigate potential risks.
• Support media engagement efforts, including tracking opportunities, maintaining reporter relationships and helping advance outreach programs.
• Assist with events and external engagements, including logistics, planning, on-site support and helping to staff senior leaders at key events.
• Serve as a triage point for the team, helping route incoming requests, coordinate follow-up and ensure senior team members are focused on the highest-priority work.
• Draft and edit communications materials, including briefing documents, key messages, backgrounders, timelines and other internal and external materials.
• Help monitor the policy, business and media environment to identify opportunities, emerging issues and reputational risks.
• Support cross-functional coordination with internal stakeholders across communications, government affairs, legal, policy and business teams.
• Provide reporting and analysis on communications programs, media coverage and message pull-through.

Senior Verification Engineer – HSIO Cluster, SOC

Senior Verification Engineer – ARM Fabric Unit Level

Senior AI Chip Design Engineer

Senior Chip Design Engineer

Partner Solutions Architect – Nordics

Firmware QA Engineer

Senior Verification Engineer – HSIO Cluster, SOC

Cyber Security Analyst

Senior Architect – Server Performance

Senior Chip Design Verification Engineer

Partner Solutions Architect – DACH, CEE Region

Senior System Software Engineer, OpenBMC

Physical Design Engineer

Principal Engineer – AI Agents and Systems

PR Manager, Policy Communications