NVIDIA

Designer

• Developing physical design methodologies for implementation of graphics processors and SOCs.
• Key responsibility includes developing unique and creative solutions to the state of the art physical design problems that are needed for NVIDIA chips.
• Participate in developing flow and tool methodologies for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

Senior Physical Design Methodology Engineer, Retime Flows

Communications

• Integrate new communication libraries features in AI frameworks: from PoC to performance analysis to production
• Perform deep analysis of AI workloads and frameworks to identify multi-GPU communication requirements and opportunities.
• Collaborate hands-on with teams working on the latest AI models.
• Improve AI compilers to hide communications or perform automatic fusion.
• Conduct in-depth AI workload performance characterization on multi-GPU clusters.
• Design fault-tolerant and elastic solutions for large-scale or dynamic AI workloads.
• Author custom communication or fused compute-communication kernels to showcase ultimate performance on NV platforms.
• Influence the roadmap of communication libraries - NCCL & NVSHMEM.
• Collaborate with a very dynamic team across multiple time zones.

Senior Deep Learning Framework Engineer

Mechanical Engineer

• The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Circuit designers and mask designers
• Perform physical layout for digital and mixed-signal functions like clock generators, op-amps, sensors, security circuits, power delivery circuits in state-of-the-art sub-micron CMOS technologies using Cadence tools
• You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products
• Job duties will include floor planning, custom layout and verifying against design rules and schematics
• Fill, post-processing, DRC mitigation, and foundry interactions

Senior Mask Layout Design Engineer

Engineer

• Join the Compute Developer Technology (Devtech) team to focus on research and development of techniques to accelerate leading applications in telecommunications and low-latency signal processing, high performance computing, scientific computing, data analytics, and AI.
• Perform in-depth analysis and optimization to ensure the best performance on the current and next generation of CPU, GPU, and network architectures.
• Engage directly with experts to understand and address their problems.
• Guide key application developers and contribute directly to applications.
• Develop reference codes or libraries, create and optimize core parallel algorithms and data structures.

Compute DevTech Engineer

Architect

• Build roadmaps for system-level features to address low-power, low-noise, perf/watt efficient, and stable/reliable product needs.
• Architect, design, and integrate system-level features, controllers, and policies to optimize product performance, power, and reliability/stability.
• Collaborate with architecture, ASIC, board/platform design, software/firmware, marketing, and other multi-functional teams.
• Expand power improvement initiatives to cover a wider range of products and market segments.
• Drive scalable, power-efficient, and reliable memory system solutions across diverse platforms.
• Keep track of the latest industry direction, market needs, and technology development; incorporate them into future roadmaps.

Senior System Power Management, Performance Architect

• Drive physical design integration and implementation of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level
• Drive RTL integration, synthesis, along with all physical netlist deliverables across various milestones
• Drive formal equivalence checking, netlist quality checks, asynchronous checking including clock domain crossing checks and MTBF analysis, etc.

Senior ASIC RTL Integration, Netlisting Engineer

• Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
• Be exposed and work on a variety of challenging designs (including high cell count and HS blocks).
• Resolving complex timing and congestion problems.
• Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
• Taking part in flows development.

Senior Physical Design Engineer

Backend Engineer

• Perform advanced Static Timing Analysis (STA) at a chiplet and FC level.
• Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
• Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
• Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.

Physical Design Backend STA Engineer

Full-stack Engineer

• Design and train innovative large-scale models—including generative, imitation, and reinforcement learning—to improve the planning and reasoning capabilities of our driving systems.
• Build, pre-train, and fine-tune LLM/VLM/VLA systems for deployment in real-world autonomous driving and robotics applications.
• Explore novel data generation and collection strategies to improve diversity and quality of training datasets.
• Collaborate with cross-functional teams to deploy AI models in production environments, ensuring performance, safety, and reliability standards are met.
• Integrate machine learning models directly with vehicle firmware to deliver production-quality, safety-critical software.

Senior Deep Learning Engineer – End-To-End Autonomous Driving

Application Engineer

• Lead debug test configuration and flow, driving efficient failure analysis (FA) and issue triage
• Assist partners in achieving Production Key Performance Indicators (KPIs)
• Oversee L6, L10 & L11 server production readiness
• Drive and validate ODM production readiness for L10 and L11 phases
• Serve as the primary technical point of contact for ODMs on L10 and L11 Production

Production Application Engineer

• Engage with product engineering teams to gain a comprehensive understanding of their infrastructure and data engineering use cases.
• Communicate build trade-offs effectively and construct scalable systems to meet their outstanding needs.
• Develop advanced tooling to automate the build and deployment of microservices and infrastructure components, improving efficiency and productivity.
• Proactively identify bottlenecks in the daily usage of core infrastructure and implement robust solutions to resolve them.
• Monitor the infrastructure to alert on significant events, ensuring the highest system performance and reliability level.

Senior Infrastructure Software Engineer

Solutions Engineer

• Lead and coordinate multiple engineering initiatives and workstreams related to content pipelines, tools, and runtime integration.
• Architect, implement, and productize SDKs, APIs, Blueprints, and reference pipelines.
• Collaborate closely with internal product, platform, and research teams.
• Work directly with Product Managers, Developer Relations, and Solution Architects.
• Define technical standards and documentation for content ingestion, transformation, validation, and deployment.
• Build high-quality, maintainable software with a focus on performance, adaptability, and observability in production environments.
• Provide technical leadership and mentorship to engineering teams.
• Drive project execution end-to-end.

Senior Content Solution Engineer

• Design, develop, and maintain GPU performance foundation libraries for Nsight tools with focus on high fidelity hardware events and counters.
• Develop and implement GPU assembly tests.
• Build and maintain a test validation framework written primarily in CUDA and GPU Assembly.
• Utilize emulators to debug and verify instruction events.
• Document tools use cases and data processing workflows to facilitate architectural explorations.

System Software Engineer, Profiler – GPU

Systems Engineer

• Collaborate with internal product, research, and engineering teams and external partners to define system requirements to enable fault-tolerant quantum computing
• Develop novel approaches to real-time quantum error correction and calibration supported by rigorous systems analysis for a variety of qubit modalities
• Distill product requirements to technical requirements across hardware, software, and firmware
• Develop test cases supporting technical requirements and review test implementations for correctness and completeness
• Adopt a culture of collaboration, rapid innovation, technical depth, and creative problem solving

Senior Quantum Systems Engineer – Quantum Computing

Infrastructure Engineer

• Lead a small team of senior engineers
• Build, develop, deploy, optimize, and document backend infrastructure features.
• Ensure a high level of architectural quality, performance in the developed code and features
• Debugging and fixing deficiencies
• Support members of other teams / clients as they adopt the technology developed
• Support the technology on multiple hardware platforms
• Partnering and collaborating with peers and managers