Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities
Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Requirements

Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience
12+ years of relevant work experience
A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
Experience in Verilog, System Verilog or similar HVL
Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
Python, Perl and C/C++ programming language experience

Benefits

equity
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Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

VLSIComputer ArchitectureVerilogSystem VerilogCADphysical design methodologieschip floorplanpower distributionclock distributiontiming closure

Soft Skills

communication skillsinterpersonal skillsteamwork

Certifications

Masters Degree in Electrical EngineeringMasters Degree in Computer ScienceMasters Degree in Computer Engineering