Senior Design-for-Test Engineer, ATPG
NVIDIA
Unix
Job Level
JuniorMid-Level
Tech Stack
PythonUnix
About the role
- In charge of state of the art Design for Test/ATPG flows and implementation
- Take ATPG ownership on different DFT aspects of a project: architecture & planning, pattern generation, verification and post-silicon bring up and diagnosis
- Invent and maintain automation flows that provide short test time to production
- Work closely with chip design, backend, verification, and production testing teams
- Participate in development of next-generation DFT technologies and internal DFT solutions
Requirements
- 0-2 years of experience
- B.Sc. in Electrical Engineering or Computer engineering or equivalent experience
- Strong programming skills in scripting languages
- Quick learner, proactive and self-motivated, eager to learn and contribute
- Sense of ownership, commitment, and responsibility
- Hands on DFT/ATPG knowledge & technical experience in DFT ASIC Design and in ATPG tools (preferred)
- Knowledge of DFT including scan, MBIST, LBIST, on-chip scan compression, fault models, ATPG, and fault simulation
- Experience in Mentor TestKompress ATPG tool and retargeting flow
- Programming languages: TCL, PRL, Python & Unix shell scripts
- Experience with ATE and Silicon bring-up
