DFT Engineer
NVIDIA
PythonUnix
Senior Design-for-Test Engineer, ATPG
NVIDIA
full-time
Posted on:
Origin: • 🇮🇱 Israel
Visit company websiteJob Level
Senior
Tech Stack
Unix
About the role
- Take charge of state-of-the-art Design for Test/ATPG flows and implementation
- Take full ATPG ownership end-to-end on a project, from architecture & planning to pattern generation, verification and post-silicon bring-up and diagnosis
- Invent and maintain automation flows to minimize test time to production
- Work closely with chip design, backend, verification, and production testing teams
- Participate in development of next-generation DFT technologies and post-silicon validation
- Contribute technical solutions and improvements for complex semiconductor chips
Requirements
- 5+ years of hands on DFT/ATPG experience
- Knowledge & technical experience in DFT ASIC Design and in ATPG tools
- Strong programming skills in scripting languages
- BSc. in Electrical Engineering or Computer engineering
- Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
- Knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation (ways to stand out)
- Experience in Mentor TestKompress ATPG tool and retargeting flow (ways to stand out)
- Programming languages: TCL, PRL, Phyton & Unix shell scripts (ways to stand out)
- Experience with ATE and Silicon bring-up (ways to stand out)
