Define SoC architecture for low-power platforms — CPU, GPU, memory subsystem, low-power IOs, and power management
Drive concept-level PPA trade-off analysis and lead the power/performance budget across the SoC
Architect the memory subsystem (LPDDR5/6, on-chip SRAM, bandwidth, QoS) for constrained power envelopes
Work with DL teams for evaluating and crafting workloads for low power — mapping tasks to constrained hardware; define optimization opportunities in partnership with Nvidia’s DL team.
Partner with CPU, GPU, and IO architecture teams inside NVIDIA to align on shared IPs and integration strategies
Translate customer requirements into architectural constraints; drive PRD development and requirements triage
Engage directly with customers pre-silicon to collect feedback and follow through on product decisions

Requirements

12+ years in SoC or product architecture
Master's Degree in Computer Engineering or Electrical Engineering (or equivalent experience)
Strong understanding of SoC architecture for low power mobile devices, including DVFS, power domains, and retention strategies
Experience with DL inference at the edge (TensorRT, TFLite, ONNX) and mapping workloads to constrained hardware
Track record of driving architecture decisions across multi-functional teams in a large organization

Benefits

equity
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Applicant Tracking System Keywords

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Hard Skills & Tools

SoC architecturelow-power platformsPPA trade-off analysismemory subsystemLPDDR5on-chip SRAMDL inferenceTensorRTTFLiteONNX

Soft Skills

leadershipcollaborationcustomer engagementrequirements triagefeedback collection

Certifications

Master's Degree in Computer EngineeringMaster's Degree in Electrical Engineering