Driving development of architecture and micro-architecture to improve the state-of-the-art in memory systems optimizing along the axes of performance, power efficiency, complexity, area, effort, and schedule
Performance modeling and simulation of features to improve memory system performance and efficiency
Implementing and maintaining detailed and high-level performance models
Analyzing benchmarks, application workloads, and performance simulation results to identify tradeoffs in areas of micro-architectural optimizations
Debugging performance and functional issues with high-level models, RTL simulation, and silicon

Requirements

M.S. or Ph.D. in CS, CE, or EE (or equivalent experience)
5+ years experience in SoC or memory system architecture and performance
Deep understanding of memory subsystems – caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation
Strong communication and interpersonal skills along with the ability to work in a dynamic, product oriented, distributed team
Exposure/coursework related to Digital systems and VLSI design, Computer Architecture, C/C++ programming languages
Software development experience with C++, python and/or perl
Verilog or SV/UVM are a plus.

Benefits

Eligible for equity and benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

memory systemsperformance modelingsimulationmicro-architecturedebuggingC++PythonPerlVerilogSV/UVM

Soft Skills

communication skillsinterpersonal skillsteamworkdynamic work environmentproduct-oriented mindset

Certifications

M.S. in Computer ScienceM.S. in Computer EngineeringM.S. in Electrical EngineeringPh.D. in Computer SciencePh.D. in Computer EngineeringPh.D. in Electrical Engineering