Developing Efficient physical design methodologies for implementation of graphics processors and SOCs.
Key responsibility includes developing unique and creative solutions to the state-of-the-art physical design problems to improve PPA
Knowledge and experience to formulate and develop with ML-based solutions
Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis and back-end verification across multiple projects along with chip floorplan, power and clock distribution, chip assembly.
Data based analysis and algorithmic solutions for PPA check and improvement.

Requirements

MS in Electrical, Computer Engineering, computer science (or equivalent experience)
5+ years’ experience in Physical Design Engineering and experience/study of ML based solution development
Proven implementation of ML-based solutions
Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
Staring knowledge of Physical design with convergence in timing/EM/IR with best PPA
Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
Familiar with various process related design issues including Design for Yield and Manufacturability, EM and IR closure and thermal management.
Solid understanding of standard industry PnR tools and analysis tools
Capable of extensive scripting to check and improve PPA

Benefits

equity
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Applicant Tracking System Keywords

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Hard Skills & Tools

Physical Design EngineeringML-based solutionsP&R (Place and Route)Timing analysisPower analysisNoise analysisBack-end verificationData analysisAlgorithmic solutionsChip floorplan

Soft Skills

Creative problem solvingCollaborationAnalytical thinkingAttention to detailCommunication

Certifications

MS in Electrical EngineeringMS in Computer EngineeringMS in Computer Science