Niobium Microsystems

Product Designer

• End-to-End Physical Implementation Leadership
• Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery
• Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow
• Architect and execute floorplanning strategies for large, hierarchical SoCs
• Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets
• Lead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys)
• Drive timing convergence across corners, modes, voltage domains, and operating conditions
• Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity
• Implement CTS and drive skew, latency, and clock power optimization
• Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC)
• Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean
• Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing
• Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout
• Provide technical leadership to a team of junior and mid-level physical designers
• Mentor, coach, and guide engineers in methodology, debug, and best practices
• Champion continuous improvement across flows, scripts, and design methodology

ASIC Physical Design Lead