ASIC Physical Design Lead

Niobium Microsystems

ASIC Physical Design Lead for Niobium Microsystems driving implementation of complex SoC designs. Collaborating with cross-functional teams to deliver high-performance, power-efficient silicon across advanced technology nodes.

Posted 7/31/2026full-timeRemote • 🇺🇸 United StatesSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in ASIC Physical Design, including Floorplanning, Place & Route, and Physical Verification. Proven ability to lead design activities, optimize for Power, Performance, and Area, and mentor teams in best practices.

Highest-signal resume keywords

ASIC Physical DesignFloorplanningPlace & RouteCadence EDA ToolsTiming Closure

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical Design MethodologyGDSII DeliveryPower OptimizationTiming AnalysisLow Power DesignDesign Rule Check (DRC)Layout Versus Schematic (LVS)Electrical Rule Check (ERC)Scan InsertionBIST Structures

Soft Skills

Technical LeadershipMentoringCollaborationContinuous ImprovementCoaching

Tools & Technologies

CadenceSynopsysEDA Tools

Industry Keywords

SoC IntegrationRTL-to-GDS FlowsTapeoutAdvanced Technology NodesDesign Architecture Trade-offs

About the role

Key responsibilities & impact

End-to-End Physical Implementation Leadership
Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery
Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow
Architect and execute floorplanning strategies for large, hierarchical SoCs
Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets
Lead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys)
Drive timing convergence across corners, modes, voltage domains, and operating conditions
Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity
Implement CTS and drive skew, latency, and clock power optimization
Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC)
Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean
Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing
Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout
Provide technical leadership to a team of junior and mid-level physical designers
Mentor, coach, and guide engineers in methodology, debug, and best practices
Champion continuous improvement across flows, scripts, and design methodology

Requirements

What you’ll need

8+ years of relevant experience in ASIC Physical Design
Strong track record of multiple tape-outs at advanced technology nodes (16nm → 3nm preferred)
Deep expertise in Floorplanning, Place & Route, CTS, STA/Timing Closure, Physical verification & sign-off, Low power design and UPF
Strong hands on proficiency with Cadence and/or Synopsys physical design toolchains
Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities
Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans
BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field (Advanced degree preferred for leadership roles)

Benefits

Comp & perks

Competitive salaries
Equity in the form of Incentive Stock Options (ISO)
Employer paid medical insurance plan
Health Savings Account (HSA) with employer contributions
Dental and vision reimbursement account (HRA)
401(k) retirement plan with employer match
Flexible work location with remote options
Flexible time off