Mobileye EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving.
Physical Design group operates in a startup-like environment with technical expertise, execution & responsibility.
Each Physical Design engineer has E2E responsibility from definition, execution & full signoffs, collaborating with design & architecture teams.
Role: Physical Design CAD Expert in Technology Methodology & Execution team, developing methodologies & flows and executing complex Subsystems/IPs for next-gen Imaging Radar SoC from definition to Tape-Out.
Responsibilities include flow & methodology development from Synthesis to Place & Route and signoff flows, planning flow releases, exploring methodologies to improve PPA & turnaround time, evaluating new tool features, hands-on block ownership, and signoff across domains.
Requirements
BSc or MSc degree in Electrical Engineering or Computer Engineering.
7+ years of experience in the Physical Design field.
Expert knowledge of the entire backend design flow from RTL to TO (Synthesis, Floorplanning, PnR , CTS , STA, EM/IR, Chip Integration).
Experience in technically leading horizontal backend activities.
Experience with flow development, exploration & tuning.
Experience with Synthesis, P&R & signoff closure on all domains.
Experience in scripting languages like Tcl/Python/Perl/TCSH & version controltools.
Experience with advanced nodes (5nm and below) - an advantage.
Team player with excellent communication skills, customer orientation, and a “can-do” attitude.