
Senior Analog Layout Engineer
Minor Hotels Europe and Americas
full-time
Posted on:
Location Type: Office
Location: San Jose • California • United States
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Salary
💰 $97,700 - $182,624 per year
Job Level
Tech Stack
About the role
- Responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
- Lead IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm, 16nm, following best practices from the industry
Requirements
- 10+ years of experience in high‑performance analog layout in advanced CMOS process
- Experience with FinFET process nodes (preferred)
- Thorough knowledge of industry‑standard EDA tools from Cadence, Mentor, and Synopsys
- Ability to set up LVS, DRC, and ERC environments and debug verification issues using Cadence and Mentor tools
- Experience with layout of high‑performance analog blocks such as analog‑to‑digital converters, references, digital‑to‑analog converters, PLLs, etc.
- Experience with floor planning, block‑level routing, and top‑level chip assembly
- Knowledge of high‑performance analog layout techniques, including common‑centroid layout, shielding, use of dummy devices, and thermal‑aware layout with consideration for electromigration
- Demonstrated experience with analog layout for silicon chips in mass production
- Experience working with distributed design teams
- Knowledge of SKILL code and layout automation
- Self‑starter with the ability to define and adhere to a schedule
- Strong written and verbal communication skills
Benefits
- Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade
- Company paid holidays
- Personal Days
- Sick Leave
- Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
- Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
- Life and disability insurance
- Employee assistance programs
- Other benefits as provided by local policy and eligibility
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
high-performance analog layoutCMOS processFinFET process nodesLVSDRCERCfloor planningblock-level routingtop-level chip assemblySKILL code
Soft Skills
self-starterschedule adherencestrong written communicationstrong verbal communication