Senior IP Logic Design Engineer

Intel Corporation

Senior IP Logic Design Engineer at Intel developing advanced technology solutions for AI and data center applications. Focused on memory systems design and integration for high-performance SoCs.

Posted 4/16/2026full-timeSanta Clara • California, Massachusetts • 🇺🇸 United StatesSenior💰 $190,610 - $269,100 per yearWebsite

About the role

Key responsibilities & impact

Develop the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs
Participate in the definition of architecture and microarchitecture features of the block being designed
Apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation
Review the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features
Support SoC customers to ensure high-quality integration and verification of the IP block
Drive quality assurance compliance for smooth IPSoC handoff
Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs
Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks
Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs
Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation
Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems
Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases
Mentor junior engineers and contribute to technical reviews and design documentation
Stay updated with emerging technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware

Requirements

What you’ll need

MS/PhD in Electrical Engineering, Computer Engineering, or related field
10+ years in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding
Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI)
Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC architectures)
Proven RTL coding experience in Verilog or SystemVerilog
Proficiency in simulation tools for performance modeling and analysis
Familiarity with physical design implications of memory fabric architectures (timing, power, area)
Experience with EDA tools for synthesis, linting, and static timing analysis

Benefits

Comp & perks

Competitive pay
Stock bonuses
Benefit programs which include health
Retirement
Vacation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

RTL codingVerilogSystemVerilogmemory coherency protocolsinterconnect technologiesperformance modelingtiming analysispower optimizationarea optimizationdesign verification

Soft Skills

mentoringcollaborationtechnical reviewscommunication

Certifications

MS in Electrical EngineeringPhD in Computer Engineering