Perform comprehensive functional verification of clock generator IPs including PLL/FLL
Proactively develop test benches, verification environments, tests, and checkers/assertions
Lead Mixed Signal Validation (MSV) activities by running AMS simulations
Replicate, root cause, and debug complex issues in the pre-silicon environment
Collaborate with architects, RTL developers, and analog schematic owners to improve verification

Requirements

Bachelor's degree in Electronics / Electrical/ Computer Engineering
3+ years of experience in Design Verification and Validation methodologies with UVM, SystemVerilog , and industry-standard EDA tools
3+ years of experience in scripting languages such as Python and Perl

Benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

Design VerificationValidation methodologiesUVMSystemVerilogscripting languagesPythonPerlAMS simulationstest benchesverification environments

Soft Skills

collaborationleadershipproblem-solvingcommunication

Certifications

Bachelor's degree in ElectronicsBachelor's degree in Electrical EngineeringBachelor's degree in Computer Engineering