Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design
Integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design
Participates in the definition of architecture and microarchitecture features of the block being designed
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence
Writes RTL and optimizes logic to qualify the design to meet power, performance, area, and timing goals
Reviews the verification plan and implementation to ensure design features are verified correctly
Works with IP providers to integrate and validate IPs at the SoC level
Drives quality assurance compliance for smooth IPSoC handoff

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
5+ years of experience in RTL design and implementation for ASIC/SoC development
Proficiency in Verilog/SystemVerilog for RTL coding and design
Experience with synthesis tools and timing closure methodologies
Understanding of clock domain crossings, power optimization, and timing closure
Exposure to SoC system integration and CPU subsystem design
Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
Knowledge of high-speed and low-power design techniques
Experience with static timing analysis (STA) tools and methodologies
Hands-on experience with formal verification tools and techniques
Basic scripting skills (Python, TCL, etc.) for automation
Experience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools

Benefits

Health insurance
Retirement plans
Flexible work arrangements
Professional development

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

RTL designVerilogSystemVerilogtiming closurepower optimizationstatic timing analysisformal verificationscriptinghigh-speed design techniqueslow-power design techniques