Collateral Device Engineer
Intel Corporation
full-time
Posted on:
Location Type: Hybrid
Location: Santa Clara • Arizona • California • United States
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Salary
💰 $190,650 - $269,150 per year
About the role
- Develop device collateral including test chip designs and product scribe line layouts
- Collaborate with Technology Development teams to establish design rules
- Manage design-rule waiver processes
- Analyze device parametric data from test chips for continuous improvement
- Provide technical guidance on design rule compliance
Requirements
- Master's degree in Electrical Engineering, Physics, or related field
- 7+ years of experience in CMOS device engineering with focus on test chip design
- Expertise in CMOS semiconductor device physics
- Experience in scribe line layout design
- Proficiency in design rule development
- Strong understanding of DTCO skills
Benefits
- Competitive pay
- Stock bonuses
- Health insurance
- Retirement plans
- Vacation
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
test chip designscribe line layout designdesign rule developmentCMOS device engineeringdevice parametric data analysisdesign rule complianceDTCO skills
Certifications
Master's degree in Electrical EngineeringMaster's degree in Physics