Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges
Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution
Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations
Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)

Requirements

US Citizenship required
Ability to obtain a US Government Security Clearance
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
5+ years of experience with advanced CMOS processes (22nm and below)
4+ years of combined experience in layout verification and parasitic extraction EDA tools
4+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting)

Benefits

Competitive compensation
Professional development in physical verification methodologies and foundry services
Opportunity to work with cutting-edge physical verification technologies for aerospace, defense, and government applications

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard skills

layout verificationparasitic extractionadvanced CMOS processesscripting languagesPythonPerlTclshell scriptingtechnical documentationtechnical training

Soft skills

collaborationproblem-solvingcommunicationleadershipcustomer support

Certifications

US Government Security Clearance