Innatera

Engineer

• Develop and maintain SystemVerilog/UVM-based verification environments at both module and SoC level;
• Write test sequences, define functional coverage models, and ensure coverage closure;
• Debug simulation results using waveform tools and collaborate with design teams to resolve issues;
• Drive constrained-random stimulus generation and continuous improvements in our verification methodology;
• Apply modern EDA tools and automate verification flows to maximize speed and quality;
• Contribute to quality assurance, release-readiness, and design-test alignment for every chip.

Staff SoC Verification Engineer

• Designing and implementing high-fidelity simulation models in modern C++ and Python that accurately mimic the behavior of our neuromorphic processors, CPUs, memory systems, and other hardware components.
• Translating complex hardware specifications into modular, efficient, and testable software models integrated within our SDK environment.
• Developing and maintaining the simulation framework, enabling both early application development and system validation before silicon is available.
• Collaborating closely with cross-functional teams (Digital Design, Firmware, and Software Tools) to ensure the simulator reflects real hardware behavior and supports continuous co-development.
• Owning the quality and performance of the simulation infrastructure — writing unit and integration tests, conducting code reviews, and improving architecture and maintainability over time.
• Contributing to the SDK’s evolution, ensuring the simulation tools are accessible, user-friendly, and valuable for both internal teams and external developers.

SDK Hardware Simulator Engineer

Senior SDK Hardware Simulation Engineer

Mechanical Engineer

• Architecting, designing, and implementing digital IP blocks and subsystems for our neuromorphic SoCs.
• Translating high-level product and algorithmic requirements into RTL-level specifications and microarchitectures.
• Owning all front-end design activities, including RTL coding (SystemVerilog/Verilog), synthesis, STA, simulation, and design documentation.
• Collaborating closely with verification and backend engineers to align functionality, constraints, and design intent.
• Defining and optimising PPA (Power, Performance, Area) goals across IPs and subsystems.
• Developing design flows and automation scripts (Python/shell scripting) to improve productivity and consistency.
• Applying low-power design techniques and contributing to overall SoC-level integration.
• Writing and maintaining documentation, including IP specifications, design intent, and integration guides.
• Mentoring junior engineers, contributing to code reviews, and fostering a culture of technical excellence and collaboration.

Staff SoC Verification Engineer

SDK Hardware Simulator Engineer

Senior SDK Hardware Simulation Engineer

Staff Digital Design Engineer