Innatera

Mechanical Engineer

• Architecting, designing, and implementing digital IP blocks and subsystems for our neuromorphic SoCs.
• Translating high-level product and algorithmic requirements into RTL-level specifications and microarchitectures.
• Owning all front-end design activities, including RTL coding (SystemVerilog/Verilog), synthesis, STA, simulation, and design documentation.
• Collaborating closely with verification and backend engineers to align functionality, constraints, and design intent.
• Defining and optimising PPA (Power, Performance, Area) goals across IPs and subsystems.
• Developing design flows and automation scripts (Python/shell scripting) to improve productivity and consistency.
• Applying low-power design techniques and contributing to overall SoC-level integration.
• Writing and maintaining documentation, including IP specifications, design intent, and integration guides.
• Mentoring junior engineers, contributing to code reviews, and fostering a culture of technical excellence and collaboration.

Staff Digital Design Engineer