Innatera

Engineer

• Develop and maintain SystemVerilog/UVM-based verification environments at both module and SoC level;
• Write test sequences, define functional coverage models, and ensure coverage closure;
• Debug simulation results using waveform tools and collaborate with design teams to resolve issues;
• Drive constrained-random stimulus generation and continuous improvements in our verification methodology;
• Apply modern EDA tools and automate verification flows to maximize speed and quality;
• Contribute to quality assurance, release-readiness, and design-test alignment for every chip.

Staff SoC Verification Engineer