EXTOLL GmbH

Engineer

• Develop and maintain UVM SystemVerilog verification environments for NoC IP
• Elaborate and work on IP and product specification documents
• Create and execute comprehensive functional verification plans
• Design, implement and continuously improve verification test benches
• Understand and debug identified errors
• Work on coverage closure and monitor daily regression runs
• Collaborate closely with the digital design team and cross-functional groups for successful product release

Staff/Principal Functional Verification Engineer

Mechanical Engineer

• As an experienced Staff/Principal Analog/Mixed-Signal Design Engineer (m/f/d), you will have the opportunity to make a significant impact on the development of our innovative products.
• You will drive the development of high-speed data interfaces.
• Take ownership of analog/mixed-signal and digital/full-custom blocks and subsystems.
• Carry out the full design and implementation of analog/mixed-signal and full-custom circuits, including schematics, testbenches and simulations.
• Collaborate with system architects to derive block-level specifications.
• Work with the verification team on model development.
• Cooperate with the layout team to guide the physical implementation.
• Provide guidance and potentially lead small design sub-teams.
• Organize and participate in the design review process.
• Work closely and cross-functionally with various groups to support a successful and timely product release.