
Staff/Principal Functional Verification Engineer
EXTOLL GmbH
full-time
Posted on:
Location Type: Hybrid
Location: Mannheim • Germany
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Job Level
Tech Stack
About the role
- Develop and maintain UVM SystemVerilog verification environments for NoC IP
- Elaborate and work on IP and product specification documents
- Create and execute comprehensive functional verification plans
- Design, implement and continuously improve verification test benches
- Understand and debug identified errors
- Work on coverage closure and monitor daily regression runs
- Collaborate closely with the digital design team and cross-functional groups for successful product release
Requirements
- B.S./M.S. degree in Electrical Engineering, Physics, Computer Engineering, Information Technology or related subject with emphasis on hardware design
- approx. 10 years of work experience, including internships
- Good knowledge of UVM SystemVerilog and SystemVerilog Assertions
- Experience with Cadence XCELIUM and vManager is a plus
- Experience in coding HDL is a plus
- Experience in script programming languages such as Python, TCL, and Bash is a plus
- Hands-on Specman-e experience is a plus
- Hands-on mentality and problem-solving capability
- Good written and oral communication skills in English required; German language would be a plus
Benefits
- Flexibility: attractive flexible working hours, above-average vacation days, a worktime account, and the possibility of mobile working (hybrid or remote work)
- Competitive Salary: competitive salary based on qualifications and skills
- Job Security: secure job in a financially stable company
- Career Opportunities: advancement opportunities with commitment, development, further training, and success
- Team Events: team events and regular exchange opportunities
- Workation: combine vacation with work abroad for up to six weeks per year
- Great Work Atmosphere: strong value orientation, good work atmosphere, appreciation, cooperation, trust, and mutual support
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
UVM SystemVerilogSystemVerilog AssertionsHDL codingPythonTCLBashSpecman-efunctional verificationverification test benchescoverage closure
Soft Skills
problem-solvingcommunicationcollaborationhands-on mentality
Certifications
B.S. degree in Electrical EngineeringM.S. degree in Electrical Engineering