Principal Digital Design Engineer, Micro-Architect
d-Matrix
full-time
Posted on:
Location Type: Hybrid
Location: Santa Clara • California • United States
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Salary
💰 $180,000 - $300,000 per year
Job Level
About the role
- Responsible for the micro-architecture and design of the AI Compute sub-system modules including Hardware Execution Engines.
- Own design, document, execute and deliver fully verified, high performance, area, and power efficient RTL.
- Design of micro-architecture and RTL, synthesis, logic and timing verification using leading edge CAD tools and semiconductor process technologies.
- Design and implement logic functions that enable efficient test and debug.
- Participate in silicon bring-up and validation for blocks owned.
Requirements
- Master’s degree in electrical engineering, Computer Engineering or Computer Science with 12 + years of meaningful work experience
- Experience in micro-architecture and RTL development (Verilog/System Verilog)
- Exposure to Computer Architecture & Arithmetic is required
- Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis
- Strong interpersonal skills and an excellent teammate
Benefits
- Offers Equity
- Offers Bonus
- Medical/Dental/Vision benefits
- 401k matching
- Inclusive rewards plan for whole self wellbeing
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
micro-architectureRTL developmentVerilogSystem Veriloglogic synthesistiming verificationASIC design flowlogic functionssilicon bring-upvalidation
Soft Skills
interpersonal skillsteamwork
Certifications
Master’s degree in electrical engineeringMaster’s degree in Computer EngineeringMaster’s degree in Computer Science