ASIC DFT Engineer, DFT/ATPG/MBIST/SCAN/JTAG
Cisco
full-time
Posted on:
Location Type: Hybrid
Location: Bangalore • India
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About the role
- Implementing Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug and diagnostics
- Development of innovative DFT IP in collaboration with multi-functional teams
- Key role in full chip design integration with testability features
- Work closely with design/design-verification and PD teams for test logic integration
- Enable validation of Test logic in all phases of implementation and post-silicon validation flows
Requirements
- Bachelor's or Master’s Degree in Electrical or Computer Engineering
- 8-10 years of related work experience
- Knowledge of DFT, test, and silicon engineering trends
- Experience with Jtag protocols, Scan insertion, ATPG
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent
- Experience working with Gate level simulation, debugging with VCS and other simulators
- Post-silicon validation and debug experience
- Ability to work with ATE patterns, P1687
- Scripting skills: Tcl, Python/Perl
Benefits
- Flexible work arrangements
- Professional development opportunities
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
Hardware Design-for-Test (DFT)Jtag protocolsScan insertionATPGGate level simulationdebuggingscriptingTclPythonPerl
Certifications
Bachelor's Degree in Electrical EngineeringBachelor's Degree in Computer EngineeringMaster’s Degree in Electrical EngineeringMaster’s Degree in Computer Engineering