ASIC Design Engineering Technical Lead
Cisco
full-time
Posted on:
Location Type: Hybrid
Location: San Jose • California • United States
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Salary
💰 $183,800 - $263,600 per year
Job Level
About the role
- Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in a range of Cisco platforms
- Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products
- Help define the process, methods, and tools for design and implementation of complex developments
- Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure
- Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets
- Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation
- Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon
- Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges
- Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team
- Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation
- Creates re-usable code that promotes efficiencies in new ways
- Influence system architecture and key design decisions across complex ASIC subsystems
Requirements
- Bachelor's degree in Electrical Engineering with 8+ years of ASIC design experience, or Master's degree in Electrical Engineering with 6+ years of ASIC design experience, or PhD in Electrical Engineering and 3+ years of ASIC design experience
- ASIC design experience, delivering silicon from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced technology nodes
- Strong expertise in high-performance RTL design using Verilog/SystemVerilog
- Deep understanding of timing closure, power optimization, and clock gating techniques
- Experience with ASIC development flows including simulation, synthesis, and static timing analysis
- 10+ years of ASIC design experience, delivering silicon from architecture and specification through tape-out preferred
- Strong documentation, problem-solving, debug and technical communication skills
- Experience working cross-functionally and collaborating with various technical teams
- Problem solver who loves to tackle new challenges and a self-starter who is highly motivated and thrives on innovative technology
Benefits
- Medical, dental and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short and long-term disability coverage
- Basic life insurance
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- Paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year for non-exempt employees
- Flexible vacation time off for exempt employees
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- Up to 80 hours of unused sick time carried forward from one calendar year to the next
- Optional 10 paid days per full calendar year to volunteer
- Annual bonuses available for non-sales roles
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
ASIC designRTL designVerilogSystem Verilogtiming closurepower optimizationclock gatingsimulationsynthesisstatic timing analysis
Soft Skills
problem-solvingtechnical communicationcollaborationmentoringdebuggingself-starterinnovationleadershiporganizational skillsattention to detail
Certifications
Bachelor's degree in Electrical EngineeringMaster's degree in Electrical EngineeringPhD in Electrical Engineering