ASIC Engineer
Cisco
full-time
Posted on:
Location Type: Hybrid
Location: Bangalore • India
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About the role
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
- Responsible for development of innovative DFT IP in collaboration with the multi-functional teams
- Key role in full chip design integration with the testability features coordinated in the RTL
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Craft solutions and debug with minimal mentorship
Requirements
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
- 8-10 years of experience
- Knowledge of the latest innovative trends in DFT, test and silicon engineering
- Experience with Jtag protocols, Scan insertion and ATPG
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets
- Experience working with Gate level simulation, debugging with VCS and other simulators
- Post-silicon validation and debug experience
- Ability to work with ATE patterns, P1687
- Strong verbal skills and ability to thrive in a multifaceted environment
- Scripting skills: Tcl, Python/Perl
Benefits
- Health insurance
- Flexible working hours
- Professional development opportunities
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
Hardware Design-for-Test (DFT)Jtag protocolsScan insertionATPGGate level simulationdebuggingscriptingTclPythonPerl
Soft Skills
strong verbal skillsability to thrive in a multifaceted environment
Certifications
Bachelor's Degree in Electrical EngineeringBachelor's Degree in Computer EngineeringMaster’s Degree in Electrical EngineeringMaster’s Degree in Computer Engineering