Cirrus Logic

Principal SoC Architect – ML Accelerators

Cirrus Logic

full-time

Posted on:

Location Type: Hybrid

Location: Austin • Texas • United States

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Job Level

Lead

About the role

  • Define the end-to-end architecture for ML accelerators and SoCs, including compute fabrics, dataflows, memory hierarchies, and integration with mixed-signal front ends.
  • Translate domain-specific requirements (voice interaction, sensor analytics, motor control) into architectural specifications and accelerator designs.
  • Lead architectural exploration of performance, power, area, and cost tradeoffs; create models and benchmarks for workload-driven analysis.
  • Collaborate closely at the instruction set and compiler/toolchain level to ensure that the ISA, micro-architecture, and runtime stack are co-optimized for ML workloads and domain-specific kernels.
  • Partner with internal engineering, startups, and research institutions to rapidly prototype candidate architectures on FPGA/ASIC platforms and validate with representative workloads.
  • Define and evaluate on-chip security architectures, including trusted execution environments (TEE), enclaves, memory partitioning, and hardware root-of-trust, ensuring robust protection for ML-enabled SoCs.
  • Evaluate external IP, startups, and research in ML accelerators; identify opportunities for partnership, licensing, or incubation.
  • Serve as a technical advisor across multiple CVL initiatives; mentor engineers, guide innovation managers, and influence long-term compute strategy.
  • Work backwards from customer problems to ensure architectures are not only performant, but also scalable, integrable, and monetizable in real-world systems.
  • Publish architectural principles, drive internal alignment around ML-enabled mixed-signal processing, and represent CVL in industry and academic forums.

Requirements

  • Ph.D or Master’s degree in Electrical Engineering, Computer Engineering, or related technical field.
  • 10+ years in SoC or accelerator design, with a focus on ML, DSP, or high-performance edge compute.
  • Deep understanding of ML accelerator architectures, including systolic arrays, SIMD/VLIW, RISC-V/ARM integration, memory subsystems, and dataflow optimization.
  • Hands-on experience defining ISAs or ISA extensions and collaborating with compiler/runtime teams to tightly couple software to hardware micro-architecture.
  • Familiarity with the architectural implications of coupling ML compute with analog/mixed-signal front ends.
  • Strong experience in architectural modeling, workload benchmarking, and system-level tradeoff analysis.
  • Expertise with simulation, emulation, FPGA prototyping, and performance modeling frameworks.
  • Proven track record of working with cross-functional teams spanning hardware, software, research, and business.
  • Ability to clearly articulate complex architectural concepts to both technical and non-technical audiences, including executives.
Benefits
  • Cirrus Logic is known for its award-winning culture
  • Built on a foundation of inclusion and fairness
  • Meaningful community engagement
  • Delivering enjoyable employee experiences
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
ML accelerator architectureSoC designDSPhigh-performance edge computesystolic arraysSIMDVLIWRISC-VARM integrationarchitectural modeling
Soft Skills
mentoringcollaborationcommunicationtechnical advisingproblem-solvinginfluencing strategyarticulating complex concepts
Certifications
Ph.D in Electrical EngineeringMaster’s degree in Electrical EngineeringMaster’s degree in Computer Engineering