Run behavioral channel simulation and analysis of high-speed wireline analog/DSP SERDES for 100G+ PAM4 standards
Model complex analog blocks, such as Transmitter, FFE, CTLE, DFE, and CDRs
Contribute to Architecture definition for SERDES links for several standards
Develop and deploy tools for analog / validation teams to speed up design and debug
Work with state-of-the-art optimization and machine learning algorithms for chip optimization
Contribute to and help develop adaptation algorithms for a variety of equalization techniques
Perform sensitivity analysis and regression simulations for various link conditions
Work with internal silicon engineering team to help perform system performance correlation between behavior models and silicon

Requirements

Masters/PhD in Electrical/Computer Engineering or Engineering Science
5+ years of experience is preferred
Previous experience with modelling critical SERDES blocks such as Transmitter, FFE, CTLE, DFE, and CDRs
Strong programming skills in MATLAB, C/C++, scripting skills in Python, Tcl, Perl
Experience working with PCIe and/or Ethernet SerDes specifications

Benefits

Comprehensive health plan
Health Spending Account (HSA)
Wellness Spending Account (WSA)
Employee Assistance Program (EAP)
Paid Vacation
Paid Holidays
Parental Leave Top-Up Program

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

behavioral channel simulationanalog modelingTransmitterFFECTLEDFECDRmachine learning algorithmssensitivity analysisregression simulations

Certifications

Masters in Electrical EngineeringPhD in Electrical EngineeringMasters in Computer EngineeringPhD in Computer EngineeringMasters in Engineering SciencePhD in Engineering Science