Alphawave Semi

Engineer

• Run behavioral channel simulation and analysis of high-speed wireline analog/DSP SERDES for 100G+ PAM4 standards
• Model complex analog blocks, such as Transmitter, FFE, CTLE, DFE, and CDRs
• Contribute to Architecture definition for SERDES links for several standards
• Develop and deploy tools for analog / validation teams to speed up design and debug
• Work with state-of-the-art optimization and machine learning algorithms for chip optimization
• Contribute to and help develop adaptation algorithms for a variety of equalization techniques
• Perform sensitivity analysis and regression simulations for various link conditions
• Work with internal silicon engineering team to help perform system performance correlation between behavior models and silicon

Systems SERDES Engineer