Staff ASIC Digital Engineer – STA, Sign-Off

Western Digital

Principal Engineer for Static Timing Analysis in Semiconductor industry at Sandisk. Leading STA methodologies and ensuring timing performance and integrity of designs.

Posted 7/21/2026full-timeRemote • 🇮🇳 IndiaLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Static Timing Analysis (STA) with a strong focus on timing closure methodologies, advanced tool utilization, and cross-functional collaboration to enhance design performance in complex IC projects.

Highest-signal resume keywords

Static Timing Analysis (STA)STA SignoffSTA Tools (Synopsys PrimeTime, Cadence Tempus)Digital Design PrinciplesAdvanced Process Nodes (5nm, 3nm)

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Timing ClosureTiming Constraints DevelopmentTiming AnalysisCritical Path IdentificationSTA Methodologies

Soft Skills

Problem-SolvingStrategic ThinkingCommunicationInterpersonal SkillsCollaboration

Tools & Technologies

Synopsys PrimeTimeCadence TempusConstraints Manager

Industry Keywords

Electrical EngineeringComputer EngineeringSemiconductor Fabrication ProcessesPhysical DesignDFT

About the role

Key responsibilities & impact

Own complete STA signoff for ASIC, providing direction and guidance to PnR team for Timing closure & Synthesis report analysis.
Work with IP & Design team for Timing constraints Development & Review activities.
Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs.
Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance.
Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes.
Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance.
Prepare and present detailed timing reports and technical documentation to stakeholders.
Foster a culture of innovation, collaboration, and continuous improvement within the STA team.

Requirements

What you’ll need

9 to 12 years of experience
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
A minimum of 8 years of experience in Static Timing Analysis.
Proven track record of successfully executing STA & Own STA signoff.
Lead complete STA activity and guided engineers to achieve the STA closure.
In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies.
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes.
Excellent problem-solving skills and the ability to think strategically and analytically.
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.
Ability to prioritize tasks and manage multiple project work simultaneously.
A proactive, results-oriented mindset with a passion for innovation and continuous improvement.
Experience with advanced process nodes (e.g. 5nm, 3nm) is highly desirable.

Benefits

Comp & perks

Employees can work remotely