Terra Quantum AG

IT Support

• Lead the Photonics technology roadmap aligned with the programme’s overall progression.
• Define go/no-go decision criteria, risk registers, and cost models for photonic integration at each process node, consistent with the programme’s existing MPW and pilot-line budgeting methodology.
• Conduct technology horizon scanning and competitive landscape analysis across silicon photonics, photonic quantum computing, and optical interconnect for AI accelerators.
• Lead the design, simulation, and characterisation of photonic components (waveguides, modulators, photodetectors, single-photon sources) compatible with the programme’s FEOL + X + BEOL process flow. Layout Execution & Tape-out Ownership: Lead complex, full-loop manual and automated layout designs and mixed-signal functions (high-speed/general I/Os, ESD structures). Drive the full tape-out process, including floor planning, waveguide routing, and mask data preparation.
• Design and simulate photonic integrated circuits for communication, sensing, or compute-related applications. Work with fabrication partners to develop layouts and ensure manufacturable designs. Collaborate with electronics, packaging, and test teams to integrate PICs into larger hardware systems.
• Execute rigorous post-layout verification (DRC, LVS, fill, density) across multiple stepping versions. Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out.
• Evaluate and specify co-integration pathways for photonic elements with the existing HZO ferroelectric and metal-oxide layers, identifying shared ALD and BEOL metal-stack process steps.
• Develop optical test and characterisation methodologies from wafer-level through to packaged sub-assembly, defining pass/fail metrics for manufacturing readiness.
• Establish and own the photonics simulation workflow, interfacing with the programme’s existing layered tool chain.
• Develop compact models and Verilog-A behavioural descriptions for photonic devices to enable system-level co-simulation with the NC-FET/memristor fabric.
• Model optical interconnect power, latency, and bandwidth budgets for hybrid electronic–photonic accelerator architectures.
• Build and lead a small specialist team as the photonics workstream scales through programme phases.
• Manage relationships with foundry partners, MPW brokers, and academic collaborators for photonic process access and IP development.
• Represent the programme at conferences, review panels, and in publications; contribute to grant and funding applications.
• Participate in programme-wide design reviews, providing photonics perspective on hybrid systolic/crossbar architecture decisions, precision formats, and KV-cache strategies.
• Contribute to the programme’s future framework, specifically on optical compute and interconnect as an enabling pillar.

Lead Photonics Integrated Circuit Engineer

Solutions Engineer

• Design, integrate, and guide deployment of LLM and machine learning solutions in customer environments, ensuring scalability and production readiness.
• Serve as the primary technical contact for customer projects, including pre-sales guidance, workshops, presentations, and long-term relationship support.
• Act as a liaison across customers, business development, engineering, research, and compliance teams to align requirements with technical delivery.
• Define and enforce standards for privacy, data governance, and ethical AI practices, ensuring compliance with regulations such as GDPR and CCPA.
• Communicate technical insights clearly to technical and non-technical stakeholders.
• Guide and mentor researchers and engineers while contributing as an individual contributor.
• Manage multiple projects in parallel to ensure quality, scalability, and customer satisfaction.
• Travel as required for customer meetings and project delivery.

Lead Photonics Integrated Circuit Engineer

AI Solutions Architect